Avnet

Product Manager/Business Developement

This role focuses on strategic supplier relationships, maximizing financial performance for assigned product lines.  Key responsibilities include managing the supplier business plan, aligning supplier goals with company objectives, participating in business reviews, identifying new opportunities, supporting price negotiations, and driving supplier performance to meet Avnet's financial targets.  The ideal candidate will have a deep understanding of industry best practices, a strong track record in supplier management, and experience in driving strategic initiatives.

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 Job Summary Supplier professional focused on the strategic leadership and relationship of company suppliers to achieve the best financial performance and relationship with assigned product lines Principal Responsibilities <ul><li>Directs and manages the supplier business plan and implementation process throughout the organization leveraging supplier strengths and resources on behalf of the supplier and communicating supplier benefits to the company.</li><li>Aligns goals and objectives of supplier with the company to ensure mutual goals and objectives are achieved.</li><li>Determines, monitors and recommends plans for the supplier, company business relationship on a tactical and strategic level.</li><li>Participates in supplier business reviews providing appropriate data and engaging in resolving issues.</li><li>Identifies and drives new supplier opportunities with particular emphasis on the development of new services that blend unique supplier resource/capability along with service/capability to create a unique value proposition.</li><li>Supports cross functional communication with the company's product groups in price negotiations and market knowledge.</li><li>Responsible for the management of activities and programs that will drive the supplier’s pro-forma performance in an effort to achieve Avnet's financial goals.</li><li>Performs analysis and reports of various program impact for the supplier.</li><li>Manages forecasting pipeline requirements and rebate projections.</li><li>Other duties as assigned. </li></ul>
Job Level Specifications <ul><li>Mastery knowledge of industry best practices and disciplines. Considered a subject matter expert within the organization and contributes to the development of new concepts, techniques and standards.</li><li>Develops solutions to highly complex and uniquely challenging situations. Assignments require extensive evaluation of alternatives and variables. Expected to make improvements to policies and procedures.</li><li>Works independently toward long-range goals and objectives. Assignments are often self-initiated using independent judgment and discretion. May act as informal team lead and/or coach less experienced team members.</li><li>Serves as consultant to management and/or internal/external spokesperson for the organization on major initiatives related to policies, plans and long-range objectives.</li><li>Actions may impact the organization and its reputation. Effects of erroneous decisions may be long-lasting, influence the future course of the organization and/or require the expenditure of extensive additional resources. </li></ul>
Work Experience <ul><li>Typically 8+ years with bachelor's or equivalent. </li></ul>
Education And Certification(s) <ul><li>Bachelor's degree or equivalent experience from which comparable knowledge and job skills can be obtained. </li></ul>
Distinguishing Characteristics <li> </li>The above statements are intended to describe the general nature and level of work being performed. They are not intended to be construed as an exhaustive list of all responsibilities, duties, and skills.
 
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If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking.As a Senior Staff Digital Design Engineer you'll be focusing on system-level digital design and integration of wireline PHY IP for high-performance SoCs and ASICs. You will be responsible for architecting and implementing digital control, adaptation, DSP, and datapath logic enabling seamless PHY operation within larger system architectures, with an emphasis on embedded microcontroller integration, bus protocols, and system validation.<h2 class="text-2xl md:text-3xl font-bold mt-10 mb-4 border-b pb-2 text-gray-800">What You Can Expect</h2><ul class="list-disc list-inside my-5 pl-5 space-y-2 text-gray-700"><li class="leading-relaxed">Architect and implement RTL for digital control, DSP blocks, digital datapath, and adaptation engines of PHY IP targeting SerDes, Die-to-Die, and Parallel Optics applications.</li><li class="leading-relaxed">Design and verify bus interfaces (APB, AHB, AXI) and register maps for microcontroller communication and firmware control.</li><li class="leading-relaxed">Collaborate closely with system architects and firmware teams to optimize PHY integration into SoC and chiplet environments.</li><li class="leading-relaxed">Drive timing closure and ensure synthesis-friendly RTL targeting system-level constraints and goals, including DSP and datapath optimizations.</li><li class="leading-relaxed">Support system bring-up activities, validation planning, and post-silicon debug with a focus on system-level interactions involving digital datapath and DSP logic.</li><li class="leading-relaxed">Mentor junior engineers and contribute to improving design methodologies for PHY system integration, including DSP and datapath design best practices.</li></ul><h2 class="text-2xl md:text-3xl font-bold mt-10 mb-4 border-b pb-2 text-gray-800">What We're Looking For</h2><ul class="list-disc list-inside my-5 pl-5 space-y-2 text-gray-700"><li class="leading-relaxed">Master’s degree +7 years or PhD +4 years in Electrical Engineering, Computer Engineering, or related fields.</li><li class="leading-relaxed">Strong RTL design expertise in Verilog/SystemVerilog, with a focus on digital control blocks, DSP, digital datapath, and bus protocols.</li><li class="leading-relaxed">Solid understanding of logic synthesis, static timing analysis (STA), constraints development, and timing closure at block and chip levels.</li><li class="leading-relaxed">Deep knowledge of CDC and RDC design principles.</li><li class="leading-relaxed">Experience integrating PHY digital blocks, including DSP and datapath modules, with embedded microcontrollers, including interrupt and event handling.</li><li class="leading-relaxed">Familiarity with scripting for design automation (Python, TCL, Perl).</li><li class="leading-relaxed">Proven problem-solving and debug experience at system level, including post-silicon validation, particularly for DSP and datapath components.</li><li class="leading-relaxed">Preferred: understanding of firmware-hardware co-design and system bring-up tools.</li></ul><h2 class="text-2xl md:text-3xl font-bold mt-10 mb-4 border-b pb-2 text-gray-800">Expected Base Pay Range (USD)</h2>124,420 - 186,400, $ per annumThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. 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Ask your recruiter during the interview process.All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at <a href="mailto:TAOps@marvell.com" target="_blank" rel="noopener noreferrer" class="text-blue-600 hover:text-blue-800 hover:underline transition-colors duration-200">TAOps@marvell.com</a>.#LI-TD1

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