A global infrastructure technology leader built on more than 60 years of innovation, collaboration and engineering excellence.&nbsp;

Broadcom

Backend Physical Design Engineer

Seeking a Backend Physical Design Engineer with 3+ years of experience in layout activities, floor-planning, partitioning, placement, clock tree synthesis, route and physical verification. Proficient in EDA tools across floorplan/partition/placement/CTS/route stages for SoC TOP. Experience with backend EDA tools like Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk is required.

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 Job Description: In this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria for achieving Right-first time silicon. Candidate should have very good experience in layout activities of block and SoC level. Should be well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification. Responsibilities include, but not limited to: <ul><li>Understanding of SoC for top-down/bottom-up physical design integration in 7nm and lower technologies</li><li>Drive Sub-block/partition decisions, floorplan for the best PPAS</li><li>Must have deep functional knowledge of P&amp;R flows, should be able to catch up quickly on internal flows, adapt.</li><li>Implement timing and functional ECO</li><li>P&amp;R, Extraction, Physical verification, work towards STA closure</li><li>Build automation flows wherever needed/adapt to existing flows for re-use</li><li>Must be proficient in any of the Cadence/Synospys/Mentor EDA tools for P&amp;R, PV, STA, ECO</li><li>Needs to be automation savvy with high expertise in one of the programming languages used in the industry</li><li>Clearly know requisites for executing his/her job and lead by example</li><li>Bring tangible improvement in TAT with better quality </li></ul>
Minimum Qualifications: <ul><li>MSEE/MSCS 3+ years (BSEE/BSCS 5+ years)</li><li>A deep understanding of backend digital design flow</li><li>Proficient in timing constraints, physical constraints</li><li>Proficient in handling EDA tools across floorplan/partition/placement/cts/route stages for SoC TOP.</li><li>Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk</li><li>Proficiency in Tcl and Perl</li><li>Excellent analytical skills</li><li>Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone </li></ul>

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