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The Senior Microarchitect will design, develop, and implement advanced memory coherency fabric systems for next-generation data center and AI chips. Responsibilities include designing scalable memory coherency protocols, developing RTL code for core components, collaborating with cross-functional teams, analyzing system performance, and mentoring junior engineers. The ideal candidate should have expertise in memory coherency protocols and interconnect technologies and also have RTL coding experience. The candidate should be able to manage and prioritize multiple tasks effectively. The role requires architectural expertise and hands-on RTL coding skills to bring cutting-edge designs to life.

Yield Development Design Analytics Engineer

<h1>Job Details:</h1><h2>Job Description:&nbsp;</h2>Do Something Wonderful!Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.Who We Are The DCAI and Silicon Eng Team (DASE) deliver leadership Xeon products to cloud and datacenter customers through development of industry leading x86 core and differentiated IPs that enhances product performance and competitiveness in both Xeon and AI platforms. IP design group within DCAI designs Coherent Fabric IP, Memory controller, NOC, PCIE and many fundamental building blocks for the Xeon server SOCs. &nbsp;Who You AreWe are seeking an experienced Senior Micro Architect to design, develop, and implement advanced memory coherency fabric systems for next-generation data center and AI chips. This role requires a unique blend of architectural expertise and hands-on RTL coding skills to bring cutting-edge designs to life. The ideal candidate will have a deep understanding of memory subsystem architecture, interconnect protocols, and coherency mechanisms, coupled with a proven ability to implement these designs at the RTL level. Your responsibilities include but not limited to:<ul><li>Architect scalable memory coherency protocols and interconnect topologies to achieve high performance and low latency for data center and AI SoCs.</li><li>Design and implement critical components of the memory fabric microarchitecture, including coherency controllers and interconnect blocks.</li><li>Develop RTL code for core components of the memory fabric, ensuring optimal performance, area, and power trade-offs.</li><li>Work closely with verification teams to create test plans and debug issues arising during pre-silicon validation.</li><li>Collaborate with cross-functional teams (physical design, software, and firmware) to ensure seamless integration of memory fabric systems.</li><li>Analyze system performance, conduct workload modeling, and optimize the architecture for target use cases.</li><li>Mentor junior engineers and contribute to technical reviews and design documentation.</li><li>Stay updated with emerging technologies and trends in memory subsystems, coherency protocols, and AI/ML hardware.</li><li>Strong problem-solving and debugging skills.</li><li>Excellent communication and collaboration abilities.</li><li>Ability to manage and prioritize multiple tasks effectively.</li></ul><h2>Qualifications:</h2>Minimum Qualifications<ul><li>Graduate of Bachelor’s Degree in Electrical Engineering, Computer Engineering, or a related field with at least 4+ years’ experience in SoC design, including significant experience in memory systems, coherency protocols, and RTL coding OR;</li></ul><ul><li>Graduate of Master’s Degree in Electrical Engineering, Computer Engineering, or a related field with at least 3+ years’ experience in SoC design, including significant experience in memory systems, coherency protocols, and RTL coding OR;</li></ul><ul><li>PhD in Electrical Engineering, Computer Engineering, or a related field.</li></ul><ul><li>Expertise in memory coherency protocols (e.g., MESI, MOESI, CXL, CCIX, CHI).</li><li>Strong knowledge of interconnect technologies (e.g., AMBA, PCIe, NoC architectures).</li><li>Proven RTL coding experience in Verilog or SystemVerilog.</li><li>Proficiency in simulation tools for performance modeling and analysis.</li><li>Familiarity with physical design implications of memory fabric architectures (timing, power, area).</li><li>Experience with EDA tools for synthesis, linting, and static timing analysis.</li></ul> Preferred Experience<ul><li>Experience with high-bandwidth memory (HBM), DDR, or other advanced memory technologies.</li><li>Knowledge in AI/ML accelerator or data center SoC design.</li><li>Knowledge of scripting languages like Python or TCL for workflow automation.</li><li>Experience with software-hardware co-design for end-to-end system optimization.</li></ul>&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;&nbsp;<h2>Job Type:</h2>Experienced Hire<h2>Shift:</h2>Shift 1 (United States of America)<h2>Primary Location:&nbsp;</h2>US, California, Santa Clara<h2>Additional Locations:</h2>US, Massachusetts, Beaver Brook<h2>Business group:</h2>The Data Center &amp; Artificial Intelligence Group (DCAI) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.<h2>Posting Statement:</h2>All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.<h2></h2><h2>Position of Trust</h2>N/ABenefits:We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. &nbsp;Find more information about all of our Amazing Benefits here:<a rel="noopener noreferrer" target="_blank" href="https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003">https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003</a>Annual Salary Range for jobs which could be performed in the US:$161,230.00-$227,620.00Salary&nbsp;range&nbsp;dependent on a number of factors including location and experience.Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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Wind River is looking for a Protocol stack / Network stack developer to join the Helix Virtualization Platform (HVP) & VxWorks development teams. The candidate will be responsible for designing, developing, implementing, and optimizing network protocols and communication stacks, and certifying safety-critical features for Aerospace, Industrial, and Automotive customers. The role involves working on the Middleware team, contributing to world-class System Software for architected hardware and software platforms. Responsibilities include designing, developing, and maintaining protocol stacks, implementing transport and network protocols, troubleshooting, and optimizing network performance.

<h3>Description</h3>
 <div class="jv-meta">
 Position at Wind River
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<div style="margin-bottom: 0.0in;line-height: normal;">JOB DESCRIPTION – Senior Engineer – NW Stack</div><div style="border: none;border-top: solid rgb(199,224,248) 1.0pt;padding: 0.0in 0.0in 0.0in 0.0in;margin-left: 0.5in;margin-right: 0.0in;"><div style="text-align: justify;line-height: 11.55pt;border: none;padding: 0.0in;margin: 7.5pt 0.0in 7.5pt 0.0in;">In a world increasingly driven by software innovation, Wind River is pioneering the technologies to accelerate the digital transformations of our customers with a new generation of Mission Critical AI Systems, with the most exacting standards for safety, security, performance, and reliability. Success will be determined by our ability to innovate with velocity and deliver at the solutions level.</div><div style="text-align: justify;line-height: 11.55pt;border: none;padding: 0.0in;margin: 7.5pt 0.0in 7.5pt 0.0in;">Wind River’s impact spans critical infrastructure domains such as&nbsp;<a href="https://www.windriver.com/markets/telecommunications/">telecommunications</a>, including 5G;&nbsp;<a href="https://www.windriver.com/markets/industrial/">industrial</a>&nbsp;(automation, sustainable energy, robotics, mining), connected&nbsp;<a href="https://www.windriver.com/markets/medical/">healthcare and medical</a>&nbsp;devices,&nbsp;<a href="https://www.windriver.com/markets/automotive/">automotive</a>&nbsp;(connected and self-driving vehicles), and&nbsp;<a href="https://www.windriver.com/markets/aerospace-defense/">aerospace &amp; defense</a>. We were recognized by VDC Research in July 2020 as&nbsp;<a href="https://www.windriver.com/news/press/pr.html?ID=22949">#1 in Edge Compute OS Platforms</a>, overtaking Microsoft as the overall commercial leader. Wind River regularly&nbsp;<a href="https://www.windriver.com/news/awards/">wins industry recognitions</a>&nbsp;for excellence in IoT security, cloud and edge computing, as well as 8 consecutive years as a “Top Work Place”. If you’re passionate about amplifying your impact on the world, in a&nbsp;<a href="https://www.windriver.com/careers/guiding-principles/">caring, respectful culture with a growth mindset</a>, come join us and help lead the way into the future of the intelligent edge!</div><div style="line-height: 15.0pt;border: none;padding: 0.0in;margin: 7.5pt 0.0in 7.5pt 0.0in;">ABOUT THE OPPORTUNITY</div><div style="text-align: justify;line-height: 15.0pt;background: white;border: none;padding: 0.0in;margin: 7.5pt 0.0in 7.5pt 0.0in;">Wind River is seeking an experienced Protocol stack / Network stack developer to join the Helix Virtualization Platform (HVP) &amp; VxWorks development teams.&nbsp; The successful candidate will be responsible for the design, development, implementation, and optimizing network protocols and communication stacks, certification of safety-critical features and functionality used by our Aerospace, Industrial and Automotive customers.&nbsp;Your expertise will work directly impact the performance, reliability, and security of our networks systems.</div><div style="text-align: justify;line-height: 15.0pt;background: white;border: none;padding: 0.0in;margin: 7.5pt 0.0in 7.5pt 0.0in;">The Middleware team is responsible for developing and improving the software eco-system around VxWorks/HVP on platforms like Arm, IA etc. next generation of applications. This contribution helps drive the development of world-class System Software for architected hardware and software platforms.</div><div style="text-align: justify;line-height: 15.0pt;background: white;border: none;padding: 0.0in;margin: 7.5pt 0.0in 7.5pt 0.0in;"></div></div><div style="border: none;border-top: solid rgb(199,224,248) 1.0pt;padding: 0.0in 0.0in 0.0in 0.0in;"><div style="line-height: 15.0pt;border: none;padding: 0.0in;margin: 7.5pt 0.0in 7.5pt 0.0in;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Responsibilities</div></div><ol><ul><li style="color: rgb(17,17,17);line-height: normal;background: white;">Design, develop, and maintain protocol stacks for various network layers (e.g., OSI model).</li><li style="color: rgb(17,17,17);line-height: normal;background: white;">Implement transport protocols (TCP, UDP) and network protocols (IP, ICMP, ARP, etc.).</li><li style="color: rgb(17,17,17);line-height: normal;background: white;">Enhance existing network stack components (e.g., socket libraries, network drivers).</li><li style="color: rgb(17,17,17);line-height: normal;background: white;">Troubleshoot and resolve network-related issues.</li><li style="color: rgb(17,17,17);line-height: normal;background: white;">Profile and optimize network performance (latency, throughput, packet loss).</li><li style="color: rgb(17,17,17);line-height: normal;background: white;">Optimize protocol performance, scalability, and reliability.</li><li style="color: rgb(17,17,17);line-height: normal;background: white;">Collaborate with cross-functional teams to ensure seamless integration of network protocols.</li><li style="color: rgb(17,17,17);line-height: normal;background: white;">Document usage guidelines, best practices, and troubleshooting tips.</li><li style="color: rgb(17,17,17);line-height: normal;background: white;">Explore emerging technologies and standards related to network protocols.</li><li style="color: rgb(17,17,17);line-height: normal;background: white;">Work closely with hardware engineers, firmware developers, and system architects.</li><li style="color: rgb(17,17,17);line-height: normal;background: white;">Participate in code reviews and contribute to architectural decisions.</li></ul></ol><div style="border: none;border-top: solid rgb(199,224,248) 1.0pt;padding: 0.0in 0.0in 0.0in 0.0in;"><div style="text-indent: 0.5in;line-height: 15.0pt;border: none;padding: 0.0in;margin: 7.5pt 0.0in 7.5pt 0.0in;">ABOUT YOU</div></div><div style="border: none;border-top: solid rgb(199,224,248) 1.0pt;padding: 0.0in 0.0in 0.0in 0.0in;margin-left: 0.5in;margin-right: 0.0in;"><div style="line-height: 15.0pt;border: none;padding: 0.0in;margin: 7.5pt 0.0in 7.5pt 0.0in;">Core Competencies &amp; Demonstrated Success</div></div><ul style="margin-top: 0.0in;"><ul style="margin-top: 0.0in;"><li style="color: rgb(38,50,56);line-height: normal;vertical-align: middle;">Experience in embedded software development.</li><li style="color: rgb(38,50,56);line-height: normal;vertical-align: middle;">Knowledge of development and verification standards like DO178C</li><li style="color: rgb(38,50,56);line-height: normal;vertical-align: middle;">Experience as a technical hands-on to work as senior individual contributor as well as mentor to juniors in the team.</li><li style="color: rgb(38,50,56);line-height: normal;vertical-align: middle;">Self-motivated with a customer-focused mindset</li><li style="color: rgb(38,50,56);line-height: normal;vertical-align: middle;">Able to develop product features in accordance with customer requirements.</li></ul></ul><div style="border: none;border-top: solid rgb(199,224,248) 1.0pt;padding: 0.0in 0.0in 0.0in 0.0in;"><div style="text-indent: 0.25in;line-height: 15.0pt;border: none;padding: 0.0in;margin: 7.5pt 0.0in 7.5pt 0.0in;">Qualifications</div></div><ul><li style="color: rgb(17,17,17);line-height: 150.0%;background: white;vertical-align: middle;">BTech / MTech degree (Computer Science, Computer/Electrical Engineering, or equivalent technical degree).</li><li style="color: rgb(17,17,17);line-height: 150.0%;background: white;vertical-align: middle;">Solid understanding of software development methodology.</li><li style="color: rgb(17,17,17);line-height: 150.0%;background: white;vertical-align: middle;">Minimum 3-5 years' experience in protocol stack or network stack development.</li><li style="color: rgb(17,17,17);line-height: 150.0%;background: white;vertical-align: middle;">Knowledge and experience of any RTOS (QNX, VxWorks, Free RTOS etc.) and embedded software development tools.</li><li style="color: rgb(17,17,17);line-height: 150.0%;background: white;vertical-align: middle;">Proficiency in developing software stacks written preferably in C, C++. </li><li style="color: rgb(17,17,17);line-height: 150.0%;background: white;">Experience with&nbsp;network protocols&nbsp;(TCP/IP, UDP, HTTP, etc.) and&nbsp;socket programming.</li><li style="color: rgb(17,17,17);line-height: 150.0%;background: white;">Familiarity with&nbsp;Linux/Unix&nbsp;networking and kernel space development is an added advantage.</li><li style="color: rgb(17,17,17);line-height: 150.0%;background: white;">Knowledge of&nbsp;security protocols&nbsp;(TLS/SSL, IPsec) and performance optimization techniques.</li><li style="color: rgb(17,17,17);line-height: 150.0%;background: white;">Strong problem-solving skills and the ability to debug complex software and system issues.</li><li style="color: rgb(38,50,56);line-height: 150.0%;vertical-align: middle;">Strong communication and collaboration skills, with the ability to work effectively in a team environment.</li></ul>

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