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Senior Manager, Product Marketing

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The Senior Manager, Product Marketing translates strategic product marketing direction into scalable programs and deliverables. This role leads a small team, owns product marketing strategy and research, and ensures consistency in go-to-market, positioning, and enablement. Key responsibilities include refining positioning, executing launch plans, leading market intelligence, managing a team, and partnering with sales and cross-functional teams to optimize product performance.

Product Manager, AI Developer Tools

<h3 class="text-xl md:text-2xl font-bold mt-8 mb-3 text-gray-800">Purpose</h3><p class="my-4 text-gray-700 leading-relaxed">The Senior Manager, Product Marketing sits between strategy and execution, translating high-level product marketing direction into scalable programs, processes, and deliverables. This role leads a small team, owns the product marketing strategy and research function, and drives rigor and consistency across go-to-market, positioning, and enablement efforts.</p><h3 class="text-xl md:text-2xl font-bold mt-8 mb-3 text-gray-800">What We Build/Manage</h3><ul class="list-disc list-inside my-5 pl-5 space-y-2 text-gray-700"><li class="leading-relaxed">Core product positioning, narratives, and competitive differentiation (in partnership with the VP)</li><li class="leading-relaxed">Ongoing product marketing research and market intelligence program</li><li class="leading-relaxed">Standardized go-to-market playbooks, templates, and processes</li><li class="leading-relaxed">Key launch workstreams and enablement deliverables</li><li class="leading-relaxed">Team workflows, priorities, and quality of outputs</li></ul><h3 class="text-xl md:text-2xl font-bold mt-8 mb-3 text-gray-800">Key Responsibilities</h3><p class="my-4 text-gray-700 leading-relaxed">Product Marketing Strategy & Positioning</p><ul class="list-disc list-inside my-5 pl-5 space-y-2 text-gray-700"><li class="leading-relaxed">Translate product marketing strategy into repeatable frameworks, templates, and deliverables</li><li class="leading-relaxed">Refine and evolve positioning, messaging, and differentiation across the portfolio</li><li class="leading-relaxed">Ensure consistency of narratives across launches, sales materials, and enablement assets</li></ul><p class="my-4 text-gray-700 leading-relaxed">Go-to-Market Execution & Operational Excellence</p><ul class="list-disc list-inside my-5 pl-5 space-y-2 text-gray-700"><li class="leading-relaxed">Own key components of launch planning, including:</li><li class="leading-relaxed">Packaging and bundling inputs</li><li class="leading-relaxed">Sales enablement frameworks</li><li class="leading-relaxed">Standardized launch checklists and timelines</li><li class="leading-relaxed">Develop and refine scalable templates for launches, collateral, and enablement materials</li><li class="leading-relaxed">Identify process gaps and recommend improvements to increase efficiency and impact</li></ul><p class="my-4 text-gray-700 leading-relaxed">Market & Product Marketing Research</p><ul class="list-disc list-inside my-5 pl-5 space-y-2 text-gray-700"><li class="leading-relaxed">Lead ongoing market intelligence efforts, including:</li><li class="leading-relaxed">Competitive tracking and battlecards</li><li class="leading-relaxed">Win/loss synthesis and trend analysis</li><li class="leading-relaxed">Customer and prospect interviews</li><li class="leading-relaxed">Market and segment insights to inform positioning and roadmap inputs</li><li class="leading-relaxed">Maintain a centralized repository of product marketing insights</li><li class="leading-relaxed">Partner with Product and Strategy teams to translate insights into actionable recommendations</li></ul><p class="my-4 text-gray-700 leading-relaxed">People Management & Team Leadership</p><ul class="list-disc list-inside my-5 pl-5 space-y-2 text-gray-700"><li class="leading-relaxed">Manage and develop a small team of product marketers</li><li class="leading-relaxed">Set priorities, review deliverables, and ensure high-quality outputs</li><li class="leading-relaxed">Coach team members on positioning, storytelling, and stakeholder management</li><li class="leading-relaxed">Balance workload and clarify ownership across workstreams</li></ul><p class="my-4 text-gray-700 leading-relaxed">Sales & Cross-Functional Partnership</p><ul class="list-disc list-inside my-5 pl-5 space-y-2 text-gray-700"><li class="leading-relaxed">Serve as a primary product marketing partner to Sales Enablement and Revenue teams</li><li class="leading-relaxed">Collaborate closely with Product, Engineering, Operations, Finance, Legal, and Communications</li><li class="leading-relaxed">Represent Product Marketing in key cross-functional forums as needed</li></ul><p class="my-4 text-gray-700 leading-relaxed">Lifecycle Support</p><ul class="list-disc list-inside my-5 pl-5 space-y-2 text-gray-700"><li class="leading-relaxed">Monitor product performance, adoption, and feedback post-launch</li><li class="leading-relaxed">Recommend optimizations to positioning, packaging, or enablement based on data and market feedback</li></ul><h3 class="text-xl md:text-2xl font-bold mt-8 mb-3 text-gray-800">Qualifications</h3><ul class="list-disc list-inside my-5 pl-5 space-y-2 text-gray-700"><li class="leading-relaxed">6–8 years of experience in B2B product marketing or closely related roles</li><li class="leading-relaxed">1–3 years of people management experience (or demonstrated leadership of peers/projects)</li><li class="leading-relaxed">Proven experience leading research-driven product marketing initiatives</li><li class="leading-relaxed">Strong analytical skills with experience synthesizing qualitative and quantitative insights</li><li class="leading-relaxed">Excellent written and verbal communication skills</li><li class="leading-relaxed">Demonstrated ability to manage complex, cross-functional initiatives</li></ul><p class="my-4 text-gray-700 leading-relaxed"><strong>About Internet Brands:</strong></p><p class="my-4 text-gray-700 leading-relaxed">At Internet Brands, we carefully consider a wide range of factors when determining compensation, including your background and experience. These considerations can cause your compensation to vary. We expect the compensation for this role to depend on your skills, qualifications, and experience. We expect this role to start with a base $90K to mid $100Ks We encourage all interested candidates to apply.</p><p class="my-4 text-gray-700 leading-relaxed">In addition to our awesome culture, we offer a comprehensive benefits package designed to support the health and well-being of you and your family. Our benefits include health insurance options such as medical, dental, and vision coverage, flexible spending accounts (FSA) for medical and dependent care, short-term and long-term disability insurance, and life and AD&D insurance. We also provide a 401(k) retirement savings plan with a company match, paid time off (PTO), paid holidays, commuter benefits as well as access to our Employee Assistance Program (EAP) and well-being coaching services. In addition, employees can take advantage of voluntary benefits such as home, auto and pet insurance, and discounted legal and financial services. For more details, feel free to inquire during the interview process.</p><p class="my-4 text-gray-700 leading-relaxed">Internet Brands®, headquartered in El Segundo, Calif, is a fully integrated online media and software services company focused on four high-value vertical categories: Health, Automotive, Legal, and Home/Travel. The company's properties and platforms include the WebMD, Medscape, and Henry Schein ONE networks, which are the global leaders in their markets; Nolo, Avvo, and Martindale, which form the largest consumer information provider in the legal market; and CarsDirect, Fodor's Travel, and many others which are leaders in their key vertical markets. Internet Brands' award-winning consumer websites lead their categories and serve more than 250 million monthly visitors, while a full range of web presence offerings has established deep, long-term relationships with SMB and enterprise clients. The company's powerful, proprietary operating platform provides the flexibility and scalability to fuel the company's continued growth. Internet Brands is a portfolio company of KKR and Warburg Pincus.</p><p class="my-4 text-gray-700 leading-relaxed">Internet Brands is an equal opportunity employer, and we welcome applicants from all backgrounds. We comply with all applicable laws and regulations, including the City of Los Angeles Fair Chance Initiative for Hiring Ordinance (FCIHO).</p><p class="my-4 text-gray-700 leading-relaxed">Notice to California residents: you can find information about our privacy practices, on: https://www.internetbrands.com/work-with-us/cpra</p>

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ASIC Engineer (N.Ex.T) - New College Graduate 2026

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NVIDIA is seeking bright new college graduates for ASIC Engineer roles in its HW Group, focusing on VLSI. Positions are available across Physical Design, Timing, DFX, PSSG, Circuit Design, SOCD, and CAD teams. Responsibilities include chip implementation, static timing analysis, design-for-test, power architecture optimization, embedded SRAM design, SOC assembly, and CAD tool development. Candidates need strong analytical, debugging, problem-solving, and communication skills, plus a solid grasp of programming, processors, operating systems, and digital design.

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<h2 class="text-2xl md:text-3xl font-bold mt-10 mb-4 border-b pb-2 text-gray-800">ASIC Engineer (N.Ex.T) - New College Graduate 2026</h2><p class="my-4 text-gray-700 leading-relaxed">India, Bengaluru</p><p class="my-4 text-gray-700 leading-relaxed">We, at NVIDIA, want to find and bring the brightest young technologists of our generation to do their life’s best work at NVIDIA. We are hiring across multiple positions in our HW Group for VLSI roles. Please find below a brief about the teams and their requirements:</p><h3 class="text-xl md:text-2xl font-bold mt-8 mb-3 text-gray-800">Physical Design Team</h3><p class="my-4 text-gray-700 leading-relaxed">The Physical Design team at NVIDIA drives end-to-end chip implementation from RTL to GDS, including floor planning, PNR, timing closure, and physical verification. They collaborate closely with design teams to optimize performance, power, and area for GPUs and ASICs across multiple platforms.</p><p class="my-4 text-gray-700 leading-relaxed"><strong>What you'll be doing:</strong></p><ul class="list-disc list-inside my-5 pl-5 space-y-2 text-gray-700"><li class="leading-relaxed">Work on all block/chip level PD activities.</li><li class="leading-relaxed">PD activities include floor plans, abstract view generation, RC extraction, PNR, STA, EM, IR DROP, DRCs & schematic to layout verification. Work in collaboration with design team for addressing design challenges.</li><li class="leading-relaxed">Help team members in debugging tool/design related issues.</li><li class="leading-relaxed">Constantly look for improvement in RTL2GDS flow to improve PPA. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention.</li><li class="leading-relaxed">Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets.</li></ul><h3 class="text-xl md:text-2xl font-bold mt-8 mb-3 text-gray-800">Timing Team:</h3><p class="my-4 text-gray-700 leading-relaxed">The ASIC Physical Design (ASIC PD) team at NVIDIA designs and validates high-performance ASICs that power next-generation computing and AI platforms. The team works on large-scale integrated and chiplet-based silicon designs, delivering industry-leading performance, power efficiency, scalability, ultra-low latency, and maximum throughput, while ensuring robust timing closure and silicon reliability at advanced technology nodes.</p><p class="my-4 text-gray-700 leading-relaxed"><strong>What you will be doing:</strong></p><ul class="list-disc list-inside my-5 pl-5 space-y-2 text-gray-700"><li class="leading-relaxed">Own and drive full-chip and/or chiplet-level Static Timing Analysis (STA) from early design stages through final timing sign-off, ensuring robust timing closure.</li><li class="leading-relaxed">Lead timing convergence across multiple design partitions in a multi-mode, multi-corner (MMMC) environment, driving closure through effective cross-team collaboration.</li><li class="leading-relaxed">Contribute to top-level floorplanning, clock architecture definition, and timing budgeting, ensuring scalable and timing-aware design implementation.</li><li class="leading-relaxed">Define, review, and maintain comprehensive timing constraints (SDC) across functional and test modes to ensure accurate and efficient timing analysis.</li><li class="leading-relaxed">Collaborate closely with RTL, PnR, and DFT teams to identify and resolve timing bottlenecks while improving overall timing Quality of Results (QoR).</li><li class="leading-relaxed">Enhance and optimize timing analysis methodologies, sign-off flows, and automation in partnership with STA methodology teams to improve efficiency and scalability.</li><li class="leading-relaxed">Perform in-depth timing analysis across diverse operating scenarios and drive optimization strategies that balance performance, power, and reliability objectives.</li></ul><h3 class="text-xl md:text-2xl font-bold mt-8 mb-3 text-gray-800">DFX Team:</h3><p class="my-4 text-gray-700 leading-relaxed">Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. This team works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.</p><p class="my-4 text-gray-700 leading-relaxed"><strong>What you'll be doing:</strong></p><ul class="list-disc list-inside my-5 pl-5 space-y-2 text-gray-700"><li class="leading-relaxed">As a member of the DFT team, you will be working on verification of state of art Memory BIST logic along with other DFT circuits like JTAG, IO BIST and ATPG.</li><li class="leading-relaxed">You will be Validating test features with a robust & scalable testplan development at unit-level and SOC/Full Chip level using verification methodologies like UVM and NVIDIA Internal tools.</li><li class="leading-relaxed">Simulating Pre-Silicon Simulation and Debug of Test functionality using standard Industry tools and sign- off on Test coverage for various products using standard coverage metrics.</li><li class="leading-relaxed">Would work on automation, flow development & improvement, coverage metrics, test execution, bug identification/fix , and Memory-test productization.</li><li class="leading-relaxed">Partner closely with our design team to understand our architecture, then collaborating with QA engineers to deliver good test coverage and improve software quality.</li></ul><h3 class="text-xl md:text-2xl font-bold mt-8 mb-3 text-gray-800">PSSG Team:</h3><p class="my-4 text-gray-700 leading-relaxed">The PSSG (Applied Power Architecture) team at NVIDIA develops innovative power features and models to optimize chip performance across consumer, server, mobile, and automotive platforms. The team works on power estimation, silicon characterization, and calibration, ensuring accurate power measurement and alignment with architecture and design goals.</p><p class="my-4 text-gray-700 leading-relaxed"><strong>What you'll be doing:</strong></p><ul class="list-disc list-inside my-5 pl-5 space-y-2 text-gray-700"><li class="leading-relaxed">Work with Arch, Design & validation teams to perform power bring up, characterize power saving & power management features</li><li class="leading-relaxed">Perform correlation of silicon KPIs with pre-si expectations.</li><li class="leading-relaxed">Work with HW and SW teams to optimize silicon power and perf/watt</li><li class="leading-relaxed">Create test plans and design experiments to accomplish goals identified for various studies</li><li class="leading-relaxed">Collect and analyze silicon power data to enable future chips’ power estimation models, design experiments to finalize modelling methods</li></ul><h3 class="text-xl md:text-2xl font-bold mt-8 mb-3 text-gray-800">Circuit Design Team:</h3><p class="my-4 text-gray-700 leading-relaxed">The Circuit Design (DIP) team at NVIDIA develops sophisticated cutting-edge digital IP, including advanced SRAM compilers, used across NVIDIA’s SoCs. They collaborate closely with system architects, design, validation, and product teams to deliver robust, scalable IP that powers next-generation semiconductor products to push the frontiers of AI innovation.</p><p class="my-4 text-gray-700 leading-relaxed"><strong>What you'll be doing:</strong></p><ul class="list-disc list-inside my-5 pl-5 space-y-2 text-gray-700"><li class="leading-relaxed">Embedded SRAM design: Transistor-level circuit design and analysis, supervising layout implementation, physical and logical verification, timing analysis, power analysis, electromigration and post-silicon learning opportunity.</li><li class="leading-relaxed">SRAM compiler development: Envisioning, defining, and coding efficient ways to automate the simultaneous assembly and validation of multiple unique SRAM macros using NVIDIA's extensive compute resources. Opportunity to use machine learning tools to solve circuit design challenges.</li><li class="leading-relaxed">Advanced development: Exploring the potential of future process nodes and developing techniques to achieve optimal power, performance, and area characteristics.</li></ul><h3 class="text-xl md:text-2xl font-bold mt-8 mb-3 text-gray-800">SOCD Team:</h3><p class="my-4 text-gray-700 leading-relaxed">The SOCD team at NVIDIA builds and integrates sophisticated Tegra SoCs, collaborating across architecture, ASIC, physical design, CAD, DFT, and packaging teams. They work on putting the SOC top-level design together and developing scalable methodologies to enable efficient, next-generation SoC development.</p><p class="my-4 text-gray-700 leading-relaxed"><strong>What you'll be doing:</strong></p><ul class="list-disc list-inside my-5 pl-5 space-y-2 text-gray-700"><li class="leading-relaxed">Drive SOC Assembly and design chip level functions for Tegra SOCs.</li><li class="leading-relaxed">Responsible for front-end design quality/correctness checks, reviews and driving those with multi-functional teams.</li><li class="leading-relaxed">Drive SOC execution across chip milestones working with all multi-functional teams to help define, track and drive complex dependencies.</li><li class="leading-relaxed">Define and develop system-level methodologies, tools, and IPs to build SOCs in an efficient and scalable manner.</li><li class="leading-relaxed">Identify difficulties and inefficiencies in the front-end chip implementation process and propose and implement ideas to solve them</li></ul><h3 class="text-xl md:text-2xl font-bold mt-8 mb-3 text-gray-800">CAD Team:</h3><p class="my-4 text-gray-700 leading-relaxed">As part of the CAD team our engineers develop and support tools for all of NVIDIA's semiconductor products. In addition, they also develop in-house tools in Design for Test (DFT) and Design for Power (DFP) using C++, Python, and TCL.</p><p class="my-4 text-gray-700 leading-relaxed"><strong>What you will be doing:</strong></p><ul class="list-disc list-inside my-5 pl-5 space-y-2 text-gray-700"><li class="leading-relaxed">Be responsible for architecting highly automated and customizable design flows using software engineering with modular design and object-oriented techniques.</li><li class="leading-relaxed">Work closely with our diverse team members on flows to provide DFT, and DFP methodologies for industry-leading chip designs.</li><li class="leading-relaxed">Support development of tools using C++/Python/TCL.</li><li class="leading-relaxed">Work cross functionally with DFT Methodology, Implementation and design teams with important DFT and power tools development tasks.</li></ul><h3 class="text-xl md:text-2xl font-bold mt-8 mb-3 text-gray-800">What we need to see:</h3><ul class="list-disc list-inside my-5 pl-5 space-y-2 text-gray-700"><li class="leading-relaxed">Pursuing B.Tech./ M.Tech</li><li class="leading-relaxed">Strong analytical skills to solve difficult problems</li><li class="leading-relaxed">Understanding of programming languages and processor</li><li class="leading-relaxed">Good grasp of operating system fundamentals & digital design concepts</li><li class="leading-relaxed">Strong debugging, problem-solving, and communication skills; ability to work in teams</li></ul>

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This assessment gives us an idea of your C++ skills- Companies that evaluate this skillset in interviews: Rockstar Games, Ubisoft, Mayhem Studios, etc.- 10 Multiple Choice questions- Average time to complete: 7 to 10 minutes

Let's assess your Data Structures! - This assessment gives us an idea of your problem solving skills using DSA- Companies that evaluate this skillset in interviews: MPL, LILA Games, GSN Games, etc.- 10 Multiple Choice questions

Data Structures and Algorithms

Let's assess your Programming Patterns! ????- This assessment gives us an idea of your code architecture skills- Companies that evaluate this skillset in interviews: Dirtcube, PTW, Playshifu, etc.

Programming Patterns

Let's assess your OOPs skills! ????- This assessment gives us an idea of your fundamental OOPS concepts and Solid principles skills- Companies that evaluate this skillset in interviews: Hitwicket, GSN Games, Tomo Club, etc.

Object Oriented Programming

Let's assess your Unity Skills ????- This assessment gives us an idea of your Unity fundamentals- Companies you can apply for after taking this assessment: Godspeed games, Salvation Games, nCore Games, etc.