MediaTek

CPU Verification Engineer

Linux Device Driver Engineer

CPU Verification

CPU Verification Engineer required with 5-12 years of experience in verification methodology. Must have strong assembly and CPU (x86/ARM/RISC-V) architecture knowledge and proficiency in C, C++, Verilog, and scripting languages. Responsibilities include test plan development, testbench design, and execution of verification plans.

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 Job Description:Key Qualifications <ul><li>Preferably BE/B.Tech/ME/M.Tech in EEE/ECE/CSE with 5-12 years of relevant industry experience.</li><li>Should have experience in verification methodology.</li><li>Architecting and development of testbench, test-bench components for ISA features, clock/reset/power features of processor.</li><li>Strong assembly and CPU (x86/ARM/RISC-V) architecture knowledge.</li><li>Strong in C, C++, Verilog, and scripting (Perl, Python) languages.</li><li>Ability to work independently and across geographies</li></ul>
 Requirement:Role and Responsibilities <ul><li>Work with CPU architects to get understand processor micro-architecture</li><li>Develop detailed test and coverage plans for ISA and micro-architecture features</li><li>Design and develop component, block and core level testbenches including stimulus engines, microarchitectural models, checkers</li><li>Build architectural tools for ISA level verification</li><li>Develop stimulus generators that scale from pre-silicon to emulation and post-silicon domain</li><li>Execute verification plans, including DV environment bring-up, regression enabling for all features under your care, debug of the test failures</li><li>Track and report DV progress using a variety of metrics, including bugs and coverage</li></ul>
 Preferred Qualifications: <ul><li>Deep knowledge in processor verification function and architecture, in areas such as cache coherence, memory ordering and consistency, prefetching, branch prediction, renaming, speculative execution, and memory translation</li><li>Knowledge in Random Instruction Sequencing (RIS) and testing associated as block/unit and chip level for proving correctness</li><li>Have lead a small team of verification engineers doing CPU verification</li><li>Advanced techniques such as formal, assertions, and silicon bring up a plus</li><li>Experience in writing test plans, portable benches, transactors, and assembly</li><li>Experience with many different verification methodologies and tools such as simulators, coverage collection, gate level simulation</li><li>Able to develop test bench and work independently on a block/unit of the design</li></ul>

 
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