Mulya Technologies

Physical Design Manager

Experienced Physical Design Manager needed to lead a team of 10+ engineers for cutting-edge SOC design. Must have strong understanding of Physical Design activities for large ASIC chips, experience with leading PD teams, and expertise in PNR tools (Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk).

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 We are looking for an experienced Physical Design Manager and deliver the next generation of cutting-edge designs Role includes managing a team of 10+ KEY RESPONSIBILITIES: <ul><li>Manage the team responsible for Synthesis, Physical Design, timing and Physical closure</li><li>Manage a large team of internal and external resources</li><li>Responsible for ensuring the completion of the SOC chip on schedule with high QOR</li><li>Physical implementation of block level and subsystem level</li><li>Contribute to Synthesis, Power Reduction, Timing Convergence Floorplan efforts of block and subsystem</li></ul>
 PREFERRED EXPERIENCE: <ul><li>Proven track record on successfully managing PD teams for complex SOC</li><li>Have an in depth understanding and experience for all Physical Design activities for a large, leading technology SOC ASIC chip</li><li>Have strong management, technical problem solving, communication and presentation skills</li><li>Great team player able to effectively interact and collaborate partner teams</li><li>Experienced with Front-End design, DFX and Physical Design Flows</li><li>Communication skills: excellent oral, written and presentation skills</li><li>Extensive Experience in handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk</li><li>Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC LVS), Crosstalk Analysis, EM/IR</li><li>Hands on experience on 7nm and sub-7nm projects</li><li>Experienced in Full Chip Floorplaning, PNR Partitioning / Bump Placement is preferred</li><li>Experience in Low power and high-performance design.</li><li>Responsible for on-time delivery of block-level layouts with exceptional quality.</li><li>Strong self-driving ability &amp; problem-solving skills with high drive for improvements</li><li>Should have excellent communication skills (both written and oral)</li></ul>
 ACADEMIC CREDENTIALS: <ul><li>BE/B.Tech/ME/M.TECH or equivalent ECE/EEE</li><li>12+ years of experience in Physical Design with at least 3+ years of experience in people management</li></ul>
 Contact:UdayMulya Technologiesmuday_bhaskar@yahoo.com"Mining The Knowledge Community"
 
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