Mulya Technologies

SENIOR LOGIC DESIGN ENGINEER – SMP Interrupt Controller

Logic MicroArchitect:

Physical Design Manager

Lead the design of an Interrupt Controller for a multi-core SMP system. Requires expertise in processor interconnect, SMP coherency, on-chip interconnect topologies, snoop protocols, latency/bandwidth optimization, queuing theory, NUMA/NUMA architecture, VHDL/Verilog, high-speed logic design, verification, validation, and physical design. Experience leading teams and agile methodologies is essential.

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 SENIOR LOGIC DESIGN ENGINEER – SMP Interrupt ControllerFortune 100 OrganizationLocation: Bangalore SENIOR LOGIC DESIGN ENGINEER – SMP Interrupt ControllerYour Role and Responsibilities <ul><li>Lead the architecture, design and development of an Interrupt Controller for a highly virtualized, multi-threaded, many-core and multi-socket SMP (symmetric multi-processor)</li><li>Develop the features, present the proposed architecture in the High level design discussions to hardware and software teams</li><li>Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, firmware, software teams to develop the feature</li><li>Signoff the Pre-silicon Design that meets all the functional, area and timing goals</li><li>Participate in silicon bring-up and validation of the hardware</li><li>Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums.</li><li>Estimate the overall effort to develop the feature</li><li>Estimate the silicon area required for the feature</li></ul>
Required Technical and Professional Expertise <ul><li>8 to 15 years of relevant experience</li><li>At least 1 generation of processor interconnect design delivery leadership (eg UPI, axi, amba, NoC).</li><li>Expertise of SMP coherency</li><li>Experience in different on-chip interconnect topologies (e.g., mesh, crossbar)</li><li>Understanding of various snoop and data network protocols</li><li>Understanding of latency &amp; bandwidth requirements and effective means of implementation</li><li>Working knowledge of queuing theory numa/nuca architecture</li><li>Proficient in HDLs- VHDL / Verilog</li><li>Experience in High speed and Power efficient logic design</li><li>Experience in working with verification, validation, physical design teams for design closure including test plan reviews and verification coverage</li><li>Good understanding of Physical Design and able to collaborate with physical design team for floor planning, wire layer usage and budgets, placement of blocks for achieving high-performance design</li><li>Experience in leading uarch, RTL design teams for feature enhancements.</li><li>Follow agile project leadership principles. Work with the team on estimation and execution plan.</li><li>Ability to quickly understand issues spanning multiple functional domains, switch context frequently and provide solutions to problems, is necessary.</li></ul>
Requirements : Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance.Preferred Technical and Professional Experience <ul><li>None</li></ul>
Preferred EducationMaster's Degree Contact:UdayMulya Technologiesmuday_bhaskar@yahoo.com"Mining The Knowledge Community"
 
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