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Utilizing PCIe protocol mainly on PHY and protocol layer, including working on designs that support PCIe. Work on verification environments like UVM, System Verilog (SV) and C. Work closely with architects, micro-architects to develop a test plan to be executed for verifying the PCIE at IP and subsystem level. Responsible for bringing up PCIe verification environments and building test benches in UVM, SV and C. Responsible for developing tests - both directed and random to exercise the PCIe IP/subsystem. Help integrate any third-party IPs into the verification environment. Develop UVM/SV/C based checks for functional correctness, including transaction order, transaction payload construction and transaction responses. Run regressions, debug any failures, collaborate with the design/IP teams to get the issues fixed and verify the fixes in a timely manner. Generate coverage for the design, analyze and close any gaps. Collaborate with SoC team in leveraging the PCIe IP verification collateral at SoC. Work closely with Firmware and Software teams to test the firmware images/ software to be run with PCIe design. Support all verification activities and the SoC through successful tape out. Assist in post-silicon debug activities once the chip comes back and guide junior engineers in the team on PCIe verification activities.

Silicon Interposer Design Flow Development Intern

<div>Utilizing PCIe protocol mainly on PHY and protocol layer, including working on designs that</div><div>support PCIe. Work on verification environments like UVM, System Verilog (SV) and C. Work</div><div>closely with architects, micro-architects to develop a test plan to be executed for verifying</div><div>the PCIE at IP and subsystem level. Responsible for bringing up PCIe verification environments</div><div>and building test benches in UVM, SV and C. Responsible for developing tests - both directed</div><div>and random to exercise the PCIe IP/subsystem. Help integrate any third-party IPs into the</div><div>verification environment. Develop UVM/SV/C based checks for functional correctness, including</div><div>transaction order, transaction payload construction and transaction responses. Run regressions,</div><div>debug any failures, collaborate with the design/IP teams to get the issues fixed and verify the</div><div>fixes in a timely manner. Generate coverage for the design, analyze and close any gaps.</div><div>Collaborate with SoC team in leveraging the PCIe IP verification collateral at SoC. Work closely</div><div>with Firmware and Software teams to test the firmware images/ software to be run</div><div>with PCIe design. Support all verification activities and the SoC through successful tape out.</div><div>Assist in post-silicon debug activities once the chip comes back and guide junior engineers in the</div><div>team on PCIe verification activities.</div><div class="section page-centered"><div><h3> Education:</h3><ul class="posting-requirements plain-list"><ul><li>Master’s or foreign equivalent in Electrical Engineering or related fields</li></ul></ul></div></div><div class="section page-centered"><div><h3>Experience: </h3><ul class="posting-requirements plain-list"><ul><li>2 years of experience in job offered or related occupation.</li></ul></ul></div></div><div class="section page-centered"><div><h3>Special Requirements: 2 years of experience must include work with the following technologies:</h3><ul class="posting-requirements plain-list"><ul><li>Creating verifications plans from the specifications using Cadence tool eplanner.</li><li>Developing interface UVC components using UVM.</li><li>Creating UVM sequences for complete verification of a module of an ASIC.</li><li>Architecting functional coverage for multiple modules of the design and completed the coverage</li><div>monitoring and closure using Cadence tool eManager.</div><li>Utilizing Verilog-OVM Methodology; Scripting Languages, e.g. Perl or Python or Tcl/Tk.</li><li>RTL Design, Coding, Simulation, Verification, and/or Place/Route; Logic Validation.</li><div><br></div></ul></ul></div></div><div class="section page-centered" data-qa="salary-range"><div>$194,500 - $202,500 a year</div><small><div>Salary</div></small></div><div class="section page-centered" data-qa="closing-description"><div><b style="font-size: 10pt">Worksite</b><span style="font-size: 10pt">:  3315 Scott Blvd., Floor 4, Santa Clara, CA 95054&nbsp;</span></div><div><b style="font-size: 10pt">Applicant&nbsp;Instructions</b><span style="font-size: 10pt">: </span>Email resume to: immigration@rivosinc.com. Must specify job code 90541 in reply. EOE.</div></div>

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Raffles Hotels & Resorts is a world-renowned luxury hospitality brand, known for its timeless elegance, legendary service, and unforgettable guest experiences. Raffles Istanbul, located in the heart of Zorlu Center, blends modern luxury with the city's rich spirit. As a Learning & Development Manager, you will be responsible for fostering a strong learning culture, staying updated with training trends, and supporting the performance evaluation and succession planning processes. You will also maintain accurate records of all training programs, including onboarding, legal, mandatory, safety, compliance, online, and service quality trainings. The role requires active participation in all Talent & Culture initiatives and activities.

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This assessment gives us an idea of your C++ skills- Companies that evaluate this skillset in interviews: Rockstar Games, Ubisoft, Mayhem Studios, etc.- 10 Multiple Choice questions- Average time to complete: 7 to 10 minutes

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