Design Verification Intern - Master's Degree (RDSS 2026)

The Central Engineering IP team provides leading-edge SerDes PHY solutions. As a member of the digital development team, the candidate will be responsible for designing, developing, and maintaining various hard macro PHY IPs. You will assist in developing and executing verification plans for high-speed interface IPs (Ethernet, SerDes, PCIe PHY), contribute to building and enhancing UVM-based verification environments, and write/debug SystemVerilog testbenches for functional and performance validation. You will also support coverage analysis, regression runs, and develop scripts to automate DV workflows.

Must Have

• Good knowledge of SystemVerilog and UVM concepts
• Good knowledge in scripting languages such as Python or Perl
• Knowledge of Object-Oriented Design principles

Good to Have

• Good programming skills, especially in C++
• Basic understanding of functional verification concepts
• Willingness to learn coverage-driven methods
• Ability to follow instructions and work collaboratively with team members
• Interest in debugging and problem-solving

Perks & Benefits

• Competitive compensation
• Great benefits
• Workstyle within an environment of shared collaboration, transparency, and inclusivity
• Tools and resources to succeed
• Opportunities to grow and develop

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The Central Engineering IP team provides leading-edge SerDes PHY solutions. As a member of the digital development team, the candidate will be responsible for designing, developing, and maintaining various hard macro PHY IPs.

What You Can Expect

• Assist in developing and executing verification plans for high-speed interface IPs (Ethernet, SerDes, PCIe PHY).
• Contribute to building and enhancing UVM-based verification environments.
• Write and debug SystemVerilog testbenches for functional and performance validation.
• Support coverage analysis and regression runs using industry-standard EDA tools.
• Develop scripts (Python/Perl) to automate DV workflows and improve efficiency.
• Collaborate with senior engineers to review test plans and analyze results.

What We're Looking For

This position is eligible for 2026 RDSS (Research and Development Substitute Services) program. Please confirm your eligibility with local district office if you are interested in applying for this role.

• Currently pursuing Master’s or Ph.D. degree in Computer Engineering, Electrical Engineering, or Computer Science.
• Good knowledge of SystemVerilog and UVM concepts.
• Good knowledge in scripting languages such as Python or Perl
• Knowledge of Object-Oriented Design principles.
• Good programming skills preferred, especially in C++

Preferred Skills

• Basic understanding of functional verification concepts and willingness to learn coverage-driven methods.
• Ability to follow instructions and work collaboratively with team members.
• Interest in debugging and problem-solving, with guidance from senior engineers.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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