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Positions are open for full-time in the areas of DFT design from unit level to chip level, involving all aspects of DFT design functions from scan, MBIST, to ATPG. Roles in the areas of CPU and SOC DFT design and verification.
Responsibilities
Define DFT strategy and methodologiesDesign the DFT features
Define test structures, debug structures, and test plans
Create test vectors or oversee their creationCollaborate with physical design team to close requirements
Validate DFT requirements are being metWork with designers to increase test coverage, debug observability and flexibility
Verify post-PD designs meet DFT requirements
Work with verification engineers, stepping in to do run tests when needed
Requirements
Good knowledge of digital logic design, microprocessor, debug feature, DFT architecture, CPU architecture, and microarchitecture
Knowledge of DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump
Knowledge of Verilog and experience with simulators and waveform debugging tools
Knowledge of Verilog / SystemVerilog
Knowledge of Python, , Shell scripting, Makefiles, TCL a plus
Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
Ability to work well in a team and be productive under aggressive schedules.
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