Memory Layout Principal Engineer

Marvell's Central Engineering (CE) team is seeking a Memory Layout Principal Engineer to develop advanced SoCs using cutting-edge process technologies. This role involves owning the entire layout process for memory compilers and custom macros, ensuring tape-out readiness through physical and reliability checks. The engineer will collaborate with design and CAD teams to optimize layouts for PPA targets across advanced nodes (7nm, 5nm, 3nm) and develop scripts to enhance efficiency. The position also includes leading layout reviews, mentoring junior engineers, and contributing to memory architecture and design methodology improvements.

Must Have

• Own the entire layout process for memory compilers and custom macros
• Ensure successful completion of all physical and reliability checks (DRC, LVS, ERC, EM/IR analysis)
• Collaborate with circuit design and CAD teams to optimize layouts for PPA targets
• Develop scripts (Perl, Python, SKILL) to improve compiler flows and verification efficiency
• Lead layout reviews, mentor junior engineers, and promote best practices
• Work with foundry teams and customers to define memory IP requirements and resolve technical issues
• Contribute to memory architecture analysis, technology roadmap, and design methodology improvements
• Bachelor's or Master's degree and/or PhD in Electrical/Electronics Engineering, Microelectronics, or related fields
• 10–12+ years of relevant professional experience
• Hands-on experience in SRAM/ROM/RF compiler layouts (bitcell, sense amp, row decoder, control, IO)
• Proven ability to design layouts from scratch: device floorplanning, signal planning, metal track planning, and full execution

Perks & Benefits

• Competitive compensation
• Great benefits
• Workstyle within an environment of shared collaboration, transparency, and inclusivity
• Tools and resources to succeed
• Opportunities to grow and develop

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Marvell’s Central Engineering (CE) team drives the development of advanced SoCs across diverse end markets, leveraging cutting-edge process technologies, analog/digital design, and advanced packaging. You will be part of the CE Memory team, delivering high-performance memory IPs that power Marvell’s next-generation products in AI, cloud data center, storage, security, and networking. This role offers the ideal environment to tackle challenges in advanced nodes, providing both breadth across engineering domains and depth within your specialization. You’ll be part of a small, agile team making a big impact across Marvell’s product portfolio.

What You Can Expect

• Own the entire layout process for memory compilers and custom macros, including floorplanning, leaf-cell creation, integration, and construction.
• Ensure successful completion of all physical and reliability checks (DRC, LVS, ERC, EM/IR analysis) for tape-out readiness.
• Collaborate with circuit design and CAD teams to optimize layouts for PPA targets across advanced nodes (7nm, 5nm, 3nm).
• Develop scripts (Perl, Python, SKILL) to improve compiler flows and verification efficiency.
• Lead layout reviews, mentor junior engineers, and promote best practices.
• Work with foundry teams and customers to define memory IP requirements and resolve technical issues.
• Contribute to memory architecture analysis, technology roadmap, and design methodology improvements.

What We're Looking For

• Bachelor's or Master's degree and/or PhD in Electrical/Electronics Engineering, Microelectronics, or related fields, with 10–12+ years of relevant professional experience.
• Hands-on experience in SRAM/ROM/RF compiler layouts (bitcell, sense amp, row decoder, control, IO).
• Proven ability to design layouts from scratch: device floorplanning, signal planning, metal track planning, and full execution.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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