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Digital Modelling and Design Engineer (f/m/d)","title":"Principal Digital Modelling and Design Engineer (f/m/d)","min_experience":5,"max_experience":null,"text_body":"\u003cdiv class=\"css-ey7qxc\"\u003e\u003cdiv data-automation-id=\"jobPostingDescription\" class=\"css-8z19x4\"\u003e\u003cp\u003e\u003cb\u003eReady to join the future of innovation in Digital Design Engineering?\u003c/b\u003e\u003c/p\u003e\u003cp\u003e\u003cbr\u003eThis opening is within the Advanced Chip Engineering (ACE) SoC Implementation Organization, a central R\u0026amp;D Design group responsible for end-to-end IC/SoC implementation of the Automotive and Industrial Automation Processors in NXP.\u003c/p\u003e\u003cp\u003e\u003cbr\u003eWe are seeking a \u003cb\u003ePrincipal Digital Modelling and Design Engineer (f/m/d)\u003c/b\u003e to join our team in Hamburg, Germany. The Hamburg SoC integration team develops complete “System on Chip” products in the domain of Radar applications and Radio Infotainment. International relocation can be accommodated for qualified candidates.\u003c/p\u003e\u003cp\u003e\u003c/p\u003e\u003cp\u003e\u003cb\u003eYour Responsibilities:\u003c/b\u003e\u003c/p\u003e\u003cul\u003e\u003cli\u003e\u003cp\u003eDesign, modelling and elaboration of abstractions that enable pre-silicon simulations of HW design using industry CAD tools\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eCreation of HW, IC/IP and SoC models using SystemC that enable early SW prototyping\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eProgramming in Matlab/Simulink: Modelling and abstraction of HW IC/IP from architectural concepts and/or requirements\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eFPGA tooling, design and verification: Creation of HW models from early RTL that enable early development\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eAutomation using scripting languages like Python or Perl\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eAnalysis, comparison and selection of different circuit topologies for optimal design: Ability to generate models and early RTL using CAD tools\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eContributing to micro-architecture, RTL design and integration of a System on Chip (SoC) or SoC sub-system, from requirements specification to tape-out and beyond\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eWorking with different functions like architecture, verification, DFT, physical implementation, post-silicon validation, etc. to provide early models that enable earlier progress\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eAbility to create models for digital circuits that include the following areas:\u003c/p\u003e\u003cul\u003e\u003cli\u003e\u003cp\u003eDigital signal processing IPs: filters, mixers, state machines, etc.\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eClock and reset infrastructure\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eOn-chip interconnect and interfaces\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eARM CPU/MCU and DSP architectures\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eDesign for low power and UPF modelling\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003e\u003cspan style=\"word-break: break-word; word-wrap: break-word; display: inline; text-decoration: inherit; hyphens: auto; -webkit-hyphens:auto; -ms-hyphens: auto; -moz-hyphens: auto;\"\u003eCommunication/control\u003c/span\u003e peripherals like PCIe, USB, DDR\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eAMS circuits and IPs including PLLs, receivers, transmitters, LDOs, amplifiers, mixersetc\u003cbr\u003e\u0026nbsp;\u003c/p\u003e\u003c/li\u003e\u003c/ul\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eDevelop and deliver signed-off verilog RTL and associated deliverables (e.g. clock/reset domain constraints, timing constraints, design documentation)\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003ePerformance, power, area and timing optimizations of your design following requirements and other constrains established by IC SoC Product architects\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eResolve design problems using knowledge of several of the following areas:\u003c/p\u003e\u003cul\u003e\u003cli\u003e\u003cp\u003eDigital signal processing architecture and design\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eClock and reset infrastructure\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eOn-chip interconnect and interfaces\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eARM CPU/MCU and DSP architectures\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eDesign for low power and UPF modelling\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003e\u003cspan style=\"word-break: break-word; word-wrap: break-word; display: inline; text-decoration: inherit; hyphens: auto; -webkit-hyphens:auto; -ms-hyphens: auto; -moz-hyphens: auto;\"\u003eCommunication/control\u003c/span\u003e peripherals like PCIe, USB, DDR\u003c/p\u003e\u003c/li\u003e\u003c/ul\u003e\u003c/li\u003e\u003c/ul\u003e\u003cp\u003e\u003c/p\u003e\u003cp\u003e\u003cb\u003eOur Team:\u003c/b\u003e\u003c/p\u003e\u003cp\u003eAs part of the Advanced Chip Engineering R\u0026amp;D team in our company, the product development of a large significant portion of NXP roadmap comes out of this organization and, consequently, there is remarkable visibility to the Corporate NXP Management team.\u003c/p\u003e\u003cp\u003eThe candidate would be integrated in a team based in Hamburg, Germany and with day-to-day interactions with other design teams based locally or abroad. Our team has a track record of more than 20 years of successful product designs and innovation.\u003c/p\u003e\u003cp\u003e\u003c/p\u003e\u003cp\u003e\u003cb\u003eYour Profile:\u003c/b\u003e\u003c/p\u003e\u003cul\u003e\u003cli\u003e\u003cp\u003eThe candidate should have significant experience with modelling using SystemC: advanced level is desired\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eModelling \u003cspan style=\"word-break: break-word; word-wrap: break-word; display: inline; text-decoration: inherit; hyphens: auto; -webkit-hyphens:auto; -ms-hyphens: auto; -moz-hyphens: auto;\"\u003eexperience\u0026nbsp;using\u003c/span\u003e programming in Matlab/Simulink is highly desired\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eExperience with FPGA tooling and design is also a must\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eProven experience with automation using several programming and scripting languages like Python or Perl\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eDigital IP or SoC design engineer with experience in all aspects of RTL design flow i.e. from specification to micro-architecture, RTL design, verification, timing analysis, area/power estimation and DFT concepts\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eThe candidate should have a strong experience in RTL design, digital signal processing, SoC integration, RTL signoff tools \u003cspan style=\"word-break: break-word; word-wrap: break-word; display: inline; text-decoration: inherit; hyphens: auto; -webkit-hyphens:auto; -ms-hyphens: auto; -moz-hyphens: auto;\"\u003e(Synthesis/CDC/RDC/Lint)\u003c/span\u003e\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eBasic knowledge of compute core (ARM or RISC-V) / DSP architectures as well as ARM-Amba bus protocols would be considered a plus\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eFluent written and verbal communication in English\u003c/p\u003e\u003c/li\u003e\u003c/ul\u003e\u003cp\u003e\u003cbr\u003eKey Soft Skills:\u003c/p\u003e\u003cul\u003e\u003cli\u003e\u003cp\u003eProficient skills in both written and verbal communication, can articulate well\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eAbility to work in a collaborative and fast-paced dynamic environment\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eCan demonstrate emotional intelligence and ability to work well as a part of local and international teams\u003cbr\u003e\u0026nbsp;\u003c/p\u003e\u003c/li\u003e\u003c/ul\u003e\u003cp\u003eEducation \u0026amp; Seniority:\u003c/p\u003e\u003cul\u003e\u003cli\u003e\u003cp\u003eDegree in Electrical Engineering or Computer Science\u003c/p\u003e\u003c/li\u003e\u003cli\u003e\u003cp\u003eAt least 5 years of experience on IP/Sub-system or SoC modelling and digital design\u003c/p\u003e\u003c/li\u003e\u003c/ul\u003e\u003cp\u003e\u003c/p\u003e\u003cp\u003e\u003ca rel=\"noopener noreferrer\" target=\"_blank\" href=\"https://www.nxp.com/company/about-nxp/worldwide-locations/germany:GERMANY\"\u003eMore information about NXP in Germany...\u003c/a\u003e\u003c/p\u003e\u003c/div\u003e\u003c/div\u003e","unmapped_location":"hamburg","location_type":"on-site","job_role":"","min_ctc":null,"max_ctc":null,"job_type":"full-time","tech_stack":["prototyping","python","perl","matlab","oops","fpga","innovation"],"slug_v2":"principal-digital-modelling-and-design-engineer-f-m-d-at-nxp-in-hamburg-hamburg-germany-1","external_job_link":"https://nxp.wd3.myworkdayjobs.com/en-US/careers/job/Principal-Digital-Modelling-and-Design-Engineer--f-m-d-_R-10056610?utm_source=outscal.com\u0026utm_campaign=outscal_jobs\u0026utm_medium=outscal_job_portal\u0026utm_content=outscal_job_apply\u0026utm_term=outscal_jobs","jobStatus":"active","activated_date":"2024-10-18T19:08:35.958Z","ai_content":{"__typename":"JobAIContent","must_have":[],"good_to_have":[],"perks":[],"summary":null},"createdAt":"2024-10-25T19:21:58.764Z","similar_jobs":[{"__typename":"SimilarJobs","title":"PDMS/E3D CAD Design Engineer (Mechanical, Electrical or HVAC)","company_id":{"__typename":"Company","display_name":"Assystems","logo":"https://outscal-lms-data.s3.ap-south-1.amazonaws.com/company-image/production/assystems/assystems_logo_10_16_2024__09_12_51.jpg","slug":"assystems"},"activated_date":"2024-10-25T14:39:11.057Z","location":{"__typename":"Location","label":"Bristol, England, United Kingdom","country":"United Kingdom","locality":"Bristol","area":"England"},"location_type":"on-site","external_job_link":"https://jobs.smartrecruiters.com/ASSYSTEM/743999994387475-pdms-e3d-cad-design-engineer-mechanical-electrical-or-hvac-?utm_source=outscal.com\u0026utm_campaign=outscal_jobs\u0026utm_medium=outscal_job_portal\u0026utm_content=outscal_job_apply\u0026utm_term=outscal_jobs","id":"671befd69c8782c7ce88bb44","_id":null,"slug_v2":"pdms-e3d-cad-design-engineer-mechanical-electrical-or-hvac-at-assystems-in-bristol-england-united-kingdom-1"},{"__typename":"SimilarJobs","title":"Senior Mechanical Design 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Services","logo":"https://outscal-assets.s3.ap-south-1.amazonaws.com/production/company/10_26_2024__08_17_52.png","slug":"next-level-business-services"},"activated_date":"2024-10-25T14:37:26.555Z","location":{"__typename":"Location","label":"Redmond, Washington, United States","country":"United States","locality":"Redmond","area":"Washington"},"location_type":"on-site","external_job_link":"https://jobs.smartrecruiters.com/NextLevelBusinessServicesInc2/92642670-ios-software-design-engineer-ios-project-manager?utm_source=outscal.com\u0026utm_campaign=outscal_jobs\u0026utm_medium=outscal_job_portal\u0026utm_content=outscal_job_apply\u0026utm_term=outscal_jobs","id":"671befd59c8782c7ce88ba46","_id":null,"slug_v2":"ios-software-design-engineer-ios-project-manager-at-nb-services-in-redmond-washington-united-states-1"},{"__typename":"SimilarJobs","title":"Civil PLT Design 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Engineer","company_id":{"__typename":"Company","display_name":"Assystems","logo":"https://outscal-lms-data.s3.ap-south-1.amazonaws.com/company-image/production/assystems/assystems_logo_10_16_2024__09_12_51.jpg","slug":"assystems"},"activated_date":"2024-10-25T14:36:24.295Z","location":{"__typename":"Location","label":"Bristol, England, United Kingdom","country":"United Kingdom","locality":"Bristol","area":"England"},"location_type":"on-site","external_job_link":"https://jobs.smartrecruiters.com/ASSYSTEM/744000006908855-senior-civil-plt-design-engineer?utm_source=