RTL design verification /ASIC design verification

4 Months ago โ€ข 3-7 Years
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About the job

SummaryBy Outscal

RTL design verification engineer needed with 3+ years of experience in Verilog/SystemVerilog and proficiency in UVM/OVM. Strong understanding of ASIC design flow and verification techniques are essential. This role contributes to the development of verification plans for complex RTL designs.

About the job

Ti๐ŸŒŸ๐‰๐จ๐ข๐ง ๐Ž๐ฎ๐ซ ๐“๐ž๐š๐ฆ ๐š๐ฌ ๐š๐ง ๐‘๐“๐‹ ๐ƒ๐ž๐ฌ๐ข๐ ๐ง ๐•๐ž๐ซ๐ข๐Ÿ๐ข๐œ๐š๐ญ๐ข๐จ๐ง ๐„๐ง๐ ๐ข๐ง๐ž๐ž๐ซ! at ARF Design๐Ÿš€

Are you passionate about #RTL_Design_verification? We're seeking a talented engineer to join our team and contribute to the semiconductor industry.

๐๐จ๐ฌ๐ข๐ญ๐ข๐จ๐ง: #RTL_Design_Verification_Engineer

๐Ÿ’ผ๐„๐ฑ๐ฉ๐ž๐ซ๐ข๐ž๐ง๐œ๐ž: 7+ Years

๐‹๐จ๐œ๐š๐ญ๐ข๐จ๐ง: #Bangalore #Bhubaneswar #hyderabad

๐‘๐ž๐ฌ๐ฉ๐จ๐ง๐ฌ๐ข๐›๐ข๐ฅ๐ข๐ญ๐ข๐ž๐ฌ::

โ–ถDevelop and execute verification plans for complex RTL designs.

โ–ถPerform functional and performance verification of design blocks.

โ–ถCollaborate with cross-functional teams to ensure successful IP component integration.

โ–ถContribute to enhancing verification methodologies and best practices.

๐๐ฎ๐š๐ฅ๐ข๐Ÿ๐ข๐œ๐š๐ญ๐ข๐จ๐ง๐ฌ:

Bachelor's or Master's degree in Electrical Engineering/Electronics & Communication Engineering or related field.

๐Ÿš€๐๐ซ๐ข๐ฆ๐š๐ซ๐ฒ ๐‘๐ž๐ช๐ฎ๐ข๐ซ๐ž๐ฆ๐ž๐ง๐ญ๐ฌ::

โ–ถMinimum of 3+ years of experience in RTL design verification.

โ–ถProficiency in Verilog/ SystemVerilog and experience with industry-standard verification methodologies (OVM/UVM).

โ–ถStrong understanding of ASIC design flow and verification techniques.

โ–ถExcellent problem-solving and debugging skills.

๐Ÿš€๐’๐ž๐œ๐จ๐ง๐๐š๐ซ๐ฒ ๐‘๐ž๐ช๐ฎ๐ข๐ซ๐ž๐ฆ๐ž๐ง๐ญ๐ฌ:

โ–ถExperience with formal verification tools and methodologies.

โ–ถFamiliarity with scripting languages (e.g., Python, Perl) for automation tasks.

โ–ถKnowledge of industry-standard protocols and interfaces (e.g., PCIe, AXI, AHB).

๐๐ž๐ง๐ž๐Ÿ๐ข๐ญ๐ฌ:

โž›Opportunities for professional growth and career advancement.

โž›Vibrant and inclusive work culture that values collaboration and innovation.

๐‘๐ž๐š๐๐ฒ ๐ญ๐จ ๐‰๐จ๐ข๐ง ๐”๐ฌ?

If you're ready to take your career to the next level and contribute to groundbreaking projects, we want to hear from you!

๐๐ฅ๐ž๐š๐ฌ๐ž ๐ฌ๐ฎ๐›๐ฆ๐ข๐ญ ๐ฒ๐จ๐ฎ๐ซ ๐ซ๐ž๐ฌ๐ฎ๐ฆ๐ž/๐‚๐• ๐ญ๐จ ๐Ÿ‘‰poojakarve@arf-design.com

๐๐จ๐ญ๐ž: Please name the file in the following format: Your Full

๐๐š๐ฆ๐ž_ ๐ƒ๐ž๐ฌ๐ข๐ ๐ง๐š๐ญ๐ข๐จ๐ง_ ๐„๐ฑ๐ฉ๐ž๐ซ๐ข๐ž๐ง๐œ๐ž.

#RTLDesign #VerificationEngineer #Semiconductor #TechJobs #EngineeringCareers #JoinOurTeam #Innovation #immediatejoiners #hiring #wfojobs #fulltimeemploymentps: Provide a summary of the role, what success in the position looks like, and how this role fits into the organization overall.

Skills: design,rtl design,asic design,semiconductor,universal verification methodology (uvm),verilog,systemverilog
โ‚น100.0K - โ‚น200.0K/yr (Outscal est.)
โ‚น150.0K/yr avg.
Bhubaneswar, Odisha, India

Odisha, India (On-Site)

Telangana, India (On-Site)

Karnataka, India (On-Site)

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