Silicon bringup and validation engineer

The Silicon Bringup and Validation Engineer is responsible for bringing up and validating the SOC subsystems in Rivos SOC design. This role requires a deep understanding of state-of-art SOC design in various aspects from physical design, logic, performance, and software. We have positions open in key components of the design such as DDR/HBM, PCIe, CPU, and data accelerator. The tasks include test generation, test infrastructure setup, bringup planning and execution, validation plan development and execution. At this time, we plan to staff the technical leads or senior technical staff positions.