SoC Logic Design Engineer

The SoC Logic Design Engineer will join Intel's Central Engineering Group (CEG), specifically the Foundry Custom Engineering (FCE) team. This role involves overseeing test chip design, foundational and hard IP, and EDA functions, as well as providing custom ASIC design services for external customers. Key responsibilities include performing DFT insertion and verification, logic design and verification, generating test patterns, consulting post-silicon stakeholders, and participating in DFT architecture definition and flow development. The position requires a Bachelor's degree and at least 1 year of experience in DFT insertion and verification.

Must Have

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science or in a related field of study
• 1+ years of hands-on experience in DFT insertion and verification
• Perform DFT insertion and verification
• Perform logic design and verification
• Generate test patterns
• Provide consultation to post-silicon key stakeholders
• Participate in the DFT Architecture definition and insertion/verification flow development

Job Details:

Job Description:

Central Engineering Group (CEG) is an organization which oversee all test chip design, all foundational and hard IP, all EDA and design platform functions for Intel Products, as well as all external IP and EDA commercial licensing. As part of this new charter, CEG will also create a new business focused on providing custom ASIC design services for external customers.

This job opportunity in CEG will be part of the Foundry Custom Engineering (FCE) group which is responsible for the Foundry Enablement in term of End-to-end design solutions helping foundry customers utilize Intel's unique IPs and design technology.

In this role you will:

• Perform DFT insertion and verification.
• Perform logic design and verification.
• Generate test patterns, and provide consultation to post-silicon key stakeholders.
• Participate in the DFT Architecture definition and insertion/verification flow development.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates

Minimum Qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science or in a related field of study.
• 1+ years of hands-on experience in DFT insertion and verification.

"Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to our staffing team at malaysia.staffing@intel.com."

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location:

Malaysia, Penang

Additional Locations:

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.