Exiger Technologies

Memory Layout Engineer

This role involves developing memory compilers layouts and Fast Cache instances layouts for next-generation cores. Must-have skills include CMOS Transistor knowledge, logic design and layout understanding, power/performance/area trade-offs, and SRAM/memory layout creation experience.

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 Experience Level 3 to 8 Years ( Mid-Level Role) Responsibilities:As Memory Layout Engineer, we will work on developing memory compilers layouts and memory Fast Cache instances layouts for our next generation Cores achieving outstanding PPA. Required Skills and Experience : We Prefer graduate or postgraduate from a University or Engineering School, in Electronic Engineering or equivalent Engineering Degree. <ul><li>We expect you to have basic understanding of CMOS Transistors, their behaviors.</li><li>We expect some basic understanding of CMOS logic design and layout.</li><li>Understanding of Power versus Performance versus Area trade-offs in typical CMOS design.</li><li>You have an engineering demeanor and Passion for Circuit layouts.</li><li>Expected to have good interpersonal skills.</li><li>Capable of creating high quality design rule driven layout</li><li>Able to review schematics with engineering and propose changes based on layout implications.</li><li>Exploring possible floor planning options and proposing improvements</li><li>Minimum 5Yrs of experience in SRAM / memory layouts creation and backend verifications including EMIR analysis.</li></ul>
Nice To Have Skills and Experience : <ul><li>You know basic scripting languages, e.g. Perl/skill.</li><li>Some Experience of working on Cadence or Synopsys flows.</li></ul>

 
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