InnoPhase IoT

Design Verification Lead

Design Verification Engineer

Sr. Staff/Principal Engineer, Digital Design

Senior Systems Software Engineer

Principal Engineer, Embedded Software

Python Build Automation Developer/ DevOps Engineer

Staff/Sr. Staff Engineer, RFIC Design

Principal Engineer, RFIC Design

Contract Embedded Software Engineer – RF Drivers

The Design Verification Lead will construct SoC level test benches, develop and execute verification plans, and implement RAL test plans. They will verify SoC using advanced methodologies, construct HW/SW Co-Verification environments, and work with the design team. The role involves debugging, reporting verification results, and utilizing constrained random verification.  The candidate will also assist in emulation, FPGA, and prototyping efforts, and implement automated verification flows using languages like Python and Perl/Shell scripts. The candidate should think through design corner cases and write relevant cover points.

Principal Engineer, Analog/Mixed-Signals Design (PMU)

<div>About InnoPhase IoT If you are keen to work with a bunch of brilliant people with various backgrounds, if you share the same value of working smart and celebrating successes, if you have enthusiasm for big technology in a small company, if your goals are to learn and experience different aspects of work--not just singing the same song every day, you’ll find your playground at Innophase IoT. We are looking for people seeking AWESOMENESS! If you’re good at what you do, you can work anywhere. If you’re the best at what you do, come work at Innophase IoT!</div><div>You will do: &nbsp;Construct SoC level test benches using verification components developed at the IP level. Test bench architecture for&nbsp; random/directed testing, stimulus generation, and checking to include custom and off the shelf VIP/UVCs. • Develop and execute SoC verification plans focused on IP block interoperability and SOC/System level. Develop and&nbsp; execute verification plans based on design specifications and collaboration with architects and designers. • Develop RAL test plan at SOC/IP level and its implementation. • Verify SoC using advanced verification methodologies. • Construct HW/SW Co-Verification environment - test-benches, use-cases, • APIs, sequences. Execute and Debug use-cases. • Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modeling (TLM), HW&nbsp; emulation/acceleration, and SW driven verification. • Work with design team to understand design intent and bring up verification plans and schedules. • You will think through design corner cases and be able to write relevant cover points. • Debug test cases and report verification result to achieve expected code/functional coverage goal. Utilize constrained&nbsp; random verification, functional coverage, code coverage and assertions to achieve goals. • Assist in emulation, FPGA, prototyping efforts. • Implement / maintain automated verification flows in languages such as Python, Perl/ Shell scripts. Required Qualifications: <ul> <li>BSEE or MSEE, with experience in ASIC development and/or FPGA prototyping</li> <li>7+ years of experience in RTL design using Verilog, SystemVerilog</li> <li>Understanding of Digital Signal Processing theory, and mapping to design</li> <li>Experience in WiFi Physical Layer, and/or other Physical layer like Cellular (WiMax, LTE, NR), Bluetooth, Zigbee, UWB, and/or other Physical layer (Ethernet) technologies</li> <li>Ability to work independently, and proactively identify and resolve issues.</li> <li>Experience with Incisive/Excellium/VCS, Verdi, Jasper/Spyglass or equivalent tools</li> <li>Experience in partitioning, synthesis, placement, timing closure for FPGA and/or ASICs</li> <li>Experience with front-end design and integration tasks including lint, CDC, synthesis, and developing timing ECOs.</li> <li>Enjoy debugging, and problem solving in a team environment.</li> </ul> Preferred Qualifications: <ul> <li>• Master’s degree in engineering (or equivalent) or Bachelor’s degree in EE/EC/CS. • 10+ years of experience in design verification - Proven experience in full chip verification from test plan development to&nbsp; tape-out sign-off. A good understanding of the complete verification life cycle (test plan, testbench through coverage&nbsp; closure)&nbsp; • Strong knowledge about multiple testbench architectures • Experience constructing chip-level System Verilog and UVM test bench environments, writing System Verilog Assertions&nbsp; (SVAs), with embedded software design and test. • Track record of successfully executing block or chip-level verification plans. • HW/SW Co-Verification experience is a plus - Developing test benches, test cases/use-cases, APIs, their execution and&nbsp; debug on a FPGA/Emulation platform. • Expertise in developing RAL using UVM methodology and able to write all the UVM component like monitor,&nbsp; scoreboard, driver, agent etc from the scratch • Proficient working knowledge of AXI-lite/AXI-Stream/APB/AHB • Excellent debug skills, with experience debugging RTL in block and/or chip-level environments. • Proficient knowledge of VHDL, System Verilog, UVM, C and scripting languages like Python, Perl and Tcl. • Proficiency with Cadence design tools/environment and cadence UVC's is plus. • Excellent communication skills, energetic and self-motivated. • Work effectively with an off-site/off-shore design/DV team</li> </ul></div><div>We bring together the best in technology,&nbsp; drive innovation to create the best ULP wireless IoT solutions and user experiences in home, building and industrial automation and wearables..&nbsp; We create career opportunities across a wide range of locations, disciplines and are at the forefront of change, thanks to our remarkable people, who bring cutting-edge products and solutions to our customers. If you share in our passion for teamwork, our vision to revolutionize the IoT industry and our goal to lead the future in technology, we want you to fast-forward your career at InnoPhase IoT. It is key to unleash the potential in every employee, every team, every leader, and the company herself. We know employees perform best when motivated, appreciated and recognized, and can be themselves. We are committed to building a culture where every voice can be heard, everyone has room for growth and can make meaningful contributions. At the end of the day, we want success not just for the company, but also for everyone who believes in the company, the vision, and the future. &nbsp;</div>

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