Synaptics Incorporated

Sr. Staff Design for Test Engineer

Sr. Systems Engineer, Wireless Modem

Staff Software Engineer

Synaptics seeks a Sr. Staff Design for Test Engineer to architect methodologies and flows for WLAN DFT, ATPG, automation, and pre/post-silicon debug.  Responsibilities include leading DFT development, ATPG test pattern generation, DFT architecture implementation (MBIST, SCAN, BSCAN), pre-silicon validation, post-silicon bring-up, and yield analysis.  The role requires deep understanding of DFT architecture, methodologies, and EDA tools (Mentor/Synopsys), proficiency in scripting (TCL/Python/Perl), and excellent debugging and communication skills. The ideal candidate will have 12+ years of experience with DFT architecture for complex SoCs and expertise in Scan/EDT, MBIST, and Boundary Scan.

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 Description Millions of people experience Synaptics every day. Our technology impacts how people see, hear, touch, and engage with a wide range of IoT applications -- at home, at work, in the car or on the go. We solve complex challenges alongside the most influential companies in the industry, using the most advanced algorithms in areas such as machine learning, biometrics, and video processing, combined with world class software and silicon development. Overview Synaptics is looking for a Sr. Staff Design for Test Engineer to join our dynamic and growing organization. You will be responsible for architecting methodologies and flows for WLAN DFT, ATPG, automation, and pre/post Silicon debug. This position reports to the VP, Silicon Engineering. Responsibilities &amp; Competencies Job Duties <ul><li>Technically Lead DFT development</li><li>Lead work on DFT flow and methodology to insert scan, mbist, ssn, ijtag / jtag, bscan</li><li>ATPG test pattern generation and simulation in RTL and GLS and PG with and without timing</li><li>Analyse DFT timing paths to define exceptions and improve architecture to ease complex DFT timing paths</li><li>Develop DFT architecture and the implementation of MBIST, SCAN, and BSCAN for multi-million gate SoCs targeted for Voice Assistant &amp; Multimedia applications</li><li>Collaborate with other team members to drive DFT methodology and flow to make it more efficient</li><li>Responsible for pre-silicon validation for all the DFT logic in block/full-chip and post-silicon bring up and yield analysis</li><li>Synthesize / optimize the DFT logic for best PPA</li><li>Responsible for the Static Timing Closure for all the test logic in block/full-chip </li></ul>
Competencies <ul><li>In depth understanding of DFT architecture and digital design concepts</li><li>Deep understanding of DFT methodologies and flows using industry standards EDA tools (Mentor / Synopsys).</li><li>Should have excellent debugging and analytical abilities. </li><li>Proficient in scripting skills (TCL / Phython / Perl) </li><li>Excellent communication, interpersonal and analytical skills, including the ability to communicate complex, interactive design concepts clearly </li><li>Ability to work with dynamic, geographically distributed teams, with the passion to become part of cross-functional teams as necessary to ensure testability </li><li>Proactive, self-starter, able to work independently in a fast-paced environment to complete projects on time with minimal guidance</li><li>Well organized with strong attention to detail; proactively ensures work is accurate</li><li>Positive attitude and work ethic; unafraid to ask questions and explore new ideas </li><li>Resourceful and able to solve complex problems through adaptation of existing technology and investigation of new technology to resolve complex problems</li><li>Willingness to mentor developing engineers </li></ul>
Qualifications (Requirements) <ul><li>Bachelor’s degree (master’s preferred) in Electrical Engineering or related field, or equivalent</li><li>12+ years of relevant working experience</li><li>Demonstrated expertise with DFT architecture – DFT planning for complex multi-million gate SoCs</li><li>Hands on expertise with Scan/EDT, MBIST, and Boundary Scan for complex multi-million gate SoCs in cutting edge process nodes.</li><li>Deep experience in the area of DFT, ATPG, Scan Insertion, MBIST, JTAG/IJAT, SSN</li><li>Experience in creating iJTAG structure in Verilog</li><li>Experience with deep debug through waveform</li><li>Direct experience using PERL scripting to create and maintain EDA tool flows</li><li>Hands-on experience on DFT insertion, pre and post silicon debug</li><li>Experience with Logic Synthesis and Static Timing Closure is a strong plus</li><li>Working knowledge of Tessent tool flow is a strong plus</li><li>Minimal travel up to 10% </li></ul>
Belief in Diversity Synaptics is an Equal Opportunity Employer committed to workforce diversity. Qualified applicants will receive consideration without regard to race, sex, sexual orientation, gender identity, national origin, color, age, religion, protected veteran or disability status, or genetic information.
 
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