Tsavorite Scalable Intelligence

Hiring Software, Firmware, RTL, Verification, FPGA and Physical Design Engineers

Tsavorite Scalable Intelligence is hiring for various software, firmware, RTL, verification, FPGA and physical design engineering roles. Experience with MLIR, LLVM, Level Zero, PCIe, CXL, and UVM is required. Join a growing team focused on accelerating enterprise AI.

Senior Software Engineer

Senior Full Stack Engineer

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Laboratory Technician

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Aquaculture Expert

Creative Talent - Visualisers and Copywriters

Video Editor

Technical Artist

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 About Tsavorite Scalable Intelligence Inc.,Tsavorite Scalable Intelligence is a semiconductor company focused on accelerating the adoption of end-to-end enterprise AI, from the edge to Zettascale systems. "Join Our Growing Team!"We're building a world-class team to drive innovation in AI Silicon &amp; Software Development, andhiring for the below positions in the US and Bangalore (India) sites. Let's share the future of AI together - take the first step towards an exciting career with us. Send your resume and a brief introduction about yourself to "jobs@tsavoritesi.com". Note: Minimum 3yrs+ work experience is required to be considered for below positions. ML SW Engineer Positions <ul><li>ML Backend Compiler Engineers with MLIR, LLVM experience</li><li>ML Runtime Engineers with Level Zero and Scheduler experience</li><li>PyTorch &amp; ONNX ML Framework Engineer</li><li>ML engineers with expertise in LLMs, CNN, RNN Inference, and Training</li><li>Performance Engineer with an in-depth understanding of ML Model Architectures and Computational requirements. Experience with performance analysis tools and methodologies.</li></ul>
 System SW and FW Engineers <ul><li>Systems SW Engineer with experience in developing health monitoring, Linux drivers, and memory checker debug frameworks.</li><li>Experience in distributed computing and building multi-tenant virtualized systems.</li><li>Systems SW Engineer with Experience in cluster management software and device discovery protocols like PAXOS, NCCL, RCCL, or any other distributed device discovery</li><li>Firmware Engineer with experience in writing device drivers for RDMA, RCoE, Ethernet, CXL, and other proprietary interfaces.</li></ul>
 RTL Design Engineers <ul><li>Hands-on experience with micro-architecture and RTL development of x86/ARM CPU Processors or high-speed custom ASICs/Accelerators.</li><li>RTL design expertise with any one of - Cache controllers, IO interfaces (PCIe, CXL, Ethernet), UCIe, Memory Controllers, Display, and Video Encoding/Transcoding IP designs.</li></ul>
 Design Verification Engineers <ul><li>Deep expertise and hands-on experience in developing UVM, SV testbench components, Checkers, Scoreboard and Stimulus</li><li>Experience in defining test plans and developing directed/constrained random tests to achieve Verification Coverage,</li><li>Prior experience and knowledge of APB/AXI/CHI bus protocols, Serial peripherals (eg: I2C, SPI), I/O Interfaces (PCIe,/CXL/ Ethernet), Memory (DDR/LPDDR/HBM)</li><li>Architectural Domain knowledge - Processors, Memory, Coherency,</li></ul>
 FPGA Engineer <ul><li>Experience in handling RTL-to-Bitstream design cycle on million+ gate FPGAs</li><li>Expertise in design partitioning, Verilog coding for FPGA fit.</li><li>Expertise in timing analysis, design optimization for timing convergence and resource utilization</li><li>Familiarity with Intel/Altera Quartus or AMD Vivado design flows</li><li>Expertise in handling standard debugging tools such as ChipScope or custom debug tools</li></ul>
Desirable experience: Expertise in configuring and bringing up hardIP/embedded ARM Cores. <ul><li>Configuring and bringup of softcore processor Microblaze (Xilinx) or Nios (Altera)</li></ul>
 Physical Design Verification Engineers <ul><li>Hands-on experience with defining methodology and setting up Physical Verification flows for both Block and SoC-level designs</li><li>Expertise in industry standard tools used for physical verification such as Mentor Calibre, CalibreDRV, V2LVS, etc.</li><li>Exposure to implementation tools like Innovus/ICC2 is a plus.</li></ul>
 Physical Design Engineers <ul><li>Experience in Physical Design implementation (from RTL to GDS) at Block or SoC designs on advanced process nodes</li><li>Expertise and experience with industry-standard CAD tools from Synopsys, Cadence or Siemens.</li><li>Experience in collaborating with RTL design and Flows teams to drive feasibility studies and converge Block/SoC designs to meet target power, frequency, and area targets.</li></ul>
 Power Delivery Network and Reliability Engineer <ul><li>Expertise in Power Grid design and in-depth knowledge of IR drop &amp; EM(electromigration) concepts</li><li>Knowledge of PDN tool algorithms and hands-on experience with industry-standard tools like Voltus and Redhawk/Redhawk-SC, Exposure to implementation tools like Innovus/ICC2 is a plus</li></ul>

 
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