Veoneer Safety Systemsis the world leader in Automotive Electronic Safety Systems. Veoneer’s scalable, best-in-class restraint control systems are saving lives by mitigating the effects of a car crash. In 2023, our products are part of more than 40 scheduled vehicle launches. To date, we have delivered more than 1 billion electronic control units and crash sensors to car manufacturers globally. The company is building on a heritage of 70 years of automotive safety development.

Venoeer

Embedded Software Development Engineer (4-6 Years)

Embedded Software Development Engineer (7-10 Years)

Network Engineer (3-6 Years)

Embedded Software Development Engineer (4-10 Years)

Veoneer exists to Protect Everyone in Every Crash, designing, manufacturing, and selling automotive safety electronics. This role involves analyzing software requirements, preparing low-level requirements and traceability documentation, architecture and detail design in EA, developing software and functional testing, performing integration test execution, and developing test scripts using J-Scripts and Python. The engineer will also be responsible for requirement gathering, design, source code programming, issue analysis and fixing, test specification preparation, and integrating AUTOSAR/BSW components and applications.

<p class="my-4 text-gray-700 leading-relaxed">Veoneer exists to Protect Everyone in Every Crash. We design, manufacture and sell the world's best automotive safety electronics.</p><h3 class="text-xl md:text-2xl font-bold mt-8 mb-3 text-gray-800">About Veoneer:</h3><p class="my-4 text-gray-700 leading-relaxed">Veoneer is a world leader, and over the years, Veoneer has delivered more than 1.1 billion electronic control units and crash sensors to car manufacturers globally.</p><p class="my-4 text-gray-700 leading-relaxed">Owned by AIP and headquartered in the U.S. Veoneer has approximately 2,550 employees in 11 countries.</p><h3 class="text-xl md:text-2xl font-bold mt-8 mb-3 text-gray-800">What you'll do:</h3><ul class="list-disc list-inside my-5 pl-5 space-y-2 text-gray-700"><li class="leading-relaxed">Analyze Software Requirements and Prepare Low level requirements and traceability documentation</li><li class="leading-relaxed">Architecture and Detail Design in EA</li><li class="leading-relaxed">Develop Software and Functional testing with specified methods and processes</li><li class="leading-relaxed">Perform Integration Test Execution for the Test Plan</li><li class="leading-relaxed">Develop Test Scripts using J-Scripts and Python Scripts</li><li class="leading-relaxed">Requirement gathering</li><li class="leading-relaxed">Design and Source code programming</li><li class="leading-relaxed">Should be able to analyses the issue reported and fix the same if required</li><li class="leading-relaxed">Test specification preparation and testing</li><li class="leading-relaxed">Integrating the AUTOSAR/ BSW components and application</li><li class="leading-relaxed">Establish and adhere to estimates in project work plan for assigned tasks</li><li class="leading-relaxed">Provide regular updates of assigned task progression to Test lead for project planning, tracking and oversight</li><li class="leading-relaxed">Identify or propose product process or infrastructure improvements</li></ul><h3 class="text-xl md:text-2xl font-bold mt-8 mb-3 text-gray-800">What you'll bring:</h3><ul class="list-disc list-inside my-5 pl-5 space-y-2 text-gray-700"><li class="leading-relaxed">Hands on Passive Safety Domain experience</li><li class="leading-relaxed">Experience in AUTOSAR based Software Development</li><li class="leading-relaxed">Good hold on Embedded C and assembly programming languages</li><li class="leading-relaxed">Experience in CAN and UDS protocol development</li><li class="leading-relaxed">Experience in RTE configuration</li><li class="leading-relaxed">Experience in Fault Handler, DEM, EOL, EDR modules development added advantage</li><li class="leading-relaxed">Experience in Cyber Security (Secure Flash, Secure Boot, HSM) modules development will be added advantage</li><li class="leading-relaxed">Hands-on experience in Software Architecture and Detail Design documentation using Enterprise Architect tool.</li><li class="leading-relaxed">Hands-on experience in Automotive development tools like Vector Geny, Da-Vinci, Tresos</li><li class="leading-relaxed">Hands-on experience in Automotive testing tools like CANoe, CANalyzer, CANstress and also on Flashing techniques.</li><li class="leading-relaxed">Experience in development of Application development like Diagnostics/ Communication stack/ MCAL/ NVRAM/ Bootloader</li><li class="leading-relaxed">Good knowledge on microcontroller architecture, memory layouts, device drivers, compiler and debuggers</li><li class="leading-relaxed">Good knowledge on Automotive protocols like CAN/ SPI</li><li class="leading-relaxed">Good Knowledge on ASPICE, ISO26262, MISRA Guidelines</li><li class="leading-relaxed">Good Knowledge on Software Debugging & Test methodology</li><li class="leading-relaxed">Experience in configuration management, change management methodologies</li></ul><h3 class="text-xl md:text-2xl font-bold mt-8 mb-3 text-gray-800">Preferred Qualification:</h3><p class="my-4 text-gray-700 leading-relaxed">BE / BTech / ME / MTech</p><h3 class="text-xl md:text-2xl font-bold mt-8 mb-3 text-gray-800">Department</h3><p class="my-4 text-gray-700 leading-relaxed">Engineering _ Embedded Software Development</p><h3 class="text-xl md:text-2xl font-bold mt-8 mb-3 text-gray-800">Locations</h3><p class="my-4 text-gray-700 leading-relaxed">Bengaluru</p><h3 class="text-xl md:text-2xl font-bold mt-8 mb-3 text-gray-800">Remote status</h3><p class="my-4 text-gray-700 leading-relaxed">Hybrid</p><h3 class="text-xl md:text-2xl font-bold mt-8 mb-3 text-gray-800">About Veoneer Safety Systems, India</h3><p class="my-4 text-gray-700 leading-relaxed"><strong>Veoneer Safety Systems</strong> is the world leader in Automotive Electronic Safety Systems.</p><p class="my-4 text-gray-700 leading-relaxed">Veoneer’s scalable, best-in-class restraint control systems are saving lives by mitigating the effects of a car crash. In 2023, our products are part of more than 40 scheduled vehicle launches. To date, we have delivered more than 1 billion electronic control units and crash sensors to car manufacturers globally.</p><p class="my-4 text-gray-700 leading-relaxed">The company is building on a heritage of 70 years of automotive safety development. Veoneer Safety Systems has 2,700 employees in 11 countries.</p>

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Marvell

Digital Intern - Masters Degree

Digital IC Design Staff Engineer

Foundry Technology - Tapeout & NPI Intern - Bachelor or Master Degree

Advanced Packaging SI/PI Engineer Intern

Analog Engineer Intern - PhD

Design Verification Intern - Bachelors Degree

ARHS

Senior .Net Developer (m/f)

Senior DevOps Developer

Western Digital

Security Manager

The Central Engineering IP team at Marvell is seeking a Digital Intern for a Masters/PhD program. This role involves designing, developing, and maintaining hard macro PHY IPs, with opportunities to work on next-generation high-speed PHY, design flows, and specifications. Responsibilities include ASIC design, verification, synthesis, static timing analysis, power analysis, and supporting integration and debug for high-speed data communication ICs.

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Senior Principal Engineer, Product Security

Principal Engineer, Customer Quality Engineering (CQE)

Senior Director, Global Account Management

Senior Staff Engineer, Analog Layout

<h3 class="text-xl md:text-2xl font-bold mt-8 mb-3 text-gray-800">About Marvell</h3><p class="my-4 text-gray-700 leading-relaxed">Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.</p><h3 class="text-xl md:text-2xl font-bold mt-8 mb-3 text-gray-800">Your Team, Your Impact</h3><p class="my-4 text-gray-700 leading-relaxed">The Central Engineering IP team provides leading-edge SerDes PHY solutions. As a member of the digital development team, the candidate will be responsible for designing, developing, and maintaining various hard macro PHY IPs. The candidate will also have an opportunity to design and develop next generation high speed PHY, design flow, and specifications.</p><h3 class="text-xl md:text-2xl font-bold mt-8 mb-3 text-gray-800">What You Can Expect</h3><p class="my-4 text-gray-700 leading-relaxed">ASIC design engineer responsible for the design, verification and evaluation of digital circuits in high-speed data communication ICs. The candidate will be involved in RTL design, verification, synthesis, and static timing analysis.</p><p class="my-4 text-gray-700 leading-relaxed">The responsibilities include but are not limited to:</p><ul class="list-disc list-inside my-5 pl-5 space-y-2 text-gray-700"><li class="leading-relaxed">Work on digital design and implementation for high speed SerDes</li><li class="leading-relaxed">Write detailed digital design specifications and implement the digital design for critical timing modules</li><li class="leading-relaxed">Conduct power analysis and implement low power designs</li><li class="leading-relaxed">Support test chip/SoC integration and cooperate with AE team for silicon debug</li><li class="leading-relaxed">Support backend team with timing analysis, timing signoff, and DFT design implementation</li></ul><h3 class="text-xl md:text-2xl font-bold mt-8 mb-3 text-gray-800">What We're Looking For</h3><ul class="list-disc list-inside my-5 pl-5 space-y-2 text-gray-700"><li class="leading-relaxed">Enrollment in a Master degree and/or PhD program in Computer Science, Electrical Engineering or related fields, or the equivalent work experience that provides knowledge and exposure to theories, principles and concepts</li><li class="leading-relaxed">Good personal communication skills and collaborative spirit</li><li class="leading-relaxed">Strong work ethic and motivation to be part of a highly competent design team</li></ul><p class="my-4 text-gray-700 leading-relaxed">Highly desirable skills:</p><ul class="list-disc list-inside my-5 pl-5 space-y-2 text-gray-700"><li class="leading-relaxed">Fundamental concepts in digital design, design verification, and timing closure (STA) in support of high-speed analog mixed-signal SerDes design</li><li class="leading-relaxed">Concepts in physical and layout design</li><li class="leading-relaxed">Excellent cross-discipline communication and interpersonal skills</li><li class="leading-relaxed">Ability to work independently and as part of a team</li><li class="leading-relaxed">Strong problem-solving and decision-making skills</li><li class="leading-relaxed">Verilog coding</li><li class="leading-relaxed">Strong Perl and Tcl scripting skill</li><li class="leading-relaxed">Synthesis using Synopsys or Cadence tools</li><li class="leading-relaxed">Timing analysis using Primetime</li><li class="leading-relaxed">DFT concepts of Scan, BIST</li></ul><h3 class="text-xl md:text-2xl font-bold mt-8 mb-3 text-gray-800">Expected Base Pay Range (USD)</h3><p class="my-4 text-gray-700 leading-relaxed">28 - 55, $ per hour.</p><p class="my-4 text-gray-700 leading-relaxed">The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.</p><h3 class="text-xl md:text-2xl font-bold mt-8 mb-3 text-gray-800">Additional Compensation and Benefit Elements</h3><p class="my-4 text-gray-700 leading-relaxed">For Internship roles, we are proud to offer the following benefits package during the internship - medical, dental and vision coverage, perks and discount programs, wellness & mental health support including coaching and therapy, paid holidays, paid volunteer days and paid sick time. Additional compensation may be available for intern PhD candidates.</p><p class="my-4 text-gray-700 leading-relaxed">All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.</p><p class="my-4 text-gray-700 leading-relaxed">Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at <a href="mailto:TAOps@marvell.com" target="_blank" rel="noopener noreferrer" class="text-blue-600 hover:text-blue-800 hover:underline transition-colors duration-200">TAOps@marvell.com</a>.</p><p class="my-4 text-gray-700 leading-relaxed"><strong><em>Interview Integrity</em></strong></p><p class="my-4 text-gray-700 leading-relaxed"><strong><em>As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.</em></strong></p><p class="my-4 text-gray-700 leading-relaxed"><strong><em>Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.</em></strong></p><p class="my-4 text-gray-700 leading-relaxed"><strong>This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.</strong></p><p class="my-4 text-gray-700 leading-relaxed">#LI-LM1</p>

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This assessment gives us an idea of your C++ skills- Companies that evaluate this skillset in interviews: Rockstar Games, Ubisoft, Mayhem Studios, etc.- 10 Multiple Choice questions- Average time to complete: 7 to 10 minutes

Let's assess your Data Structures! - This assessment gives us an idea of your problem solving skills using DSA- Companies that evaluate this skillset in interviews: MPL, LILA Games, GSN Games, etc.- 10 Multiple Choice questions

Data Structures and Algorithms

Let's assess your Programming Patterns! ????- This assessment gives us an idea of your code architecture skills- Companies that evaluate this skillset in interviews: Dirtcube, PTW, Playshifu, etc.

Programming Patterns

Let's assess your OOPs skills! ????- This assessment gives us an idea of your fundamental OOPS concepts and Solid principles skills- Companies that evaluate this skillset in interviews: Hitwicket, GSN Games, Tomo Club, etc.

Object Oriented Programming

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Embedded Software Development Engineer (4-6 Years)

Embedded Software Development Engineer (7-10 Years)

Network Engineer (3-6 Years)

Embedded Software Development Engineer (4-10 Years)

Job Details