ASIC Design for Testability Engineer, Silicon
Job Summary
Job Description
- 4+ years DFT/DFD experience
- DFT specification development
- DFT architecture experience
- EDA tool proficiency (Design Compiler, DFT Max etc.)
- Test standard and format knowledge (IEEE 1149.10, BSDL etc.)
- Post-silicon bring-up and debug
- UDFM generation experience
- STA constraints development
- Experience with MBIST, JTAG, ATPG
- Silicon validation on ATE
2 skills required
Job Details
Minimum qualifications:
- Bachelor's degree or equivalent practical experience.
- 4 years of experience in DFT/DFD flows and methodologies.
- Experience developing DFT specifications and driving DFT architecture.
Preferred qualifications:
- Experience with User Defined Fault Models (UDFM) generation like Cell-Aware and other fault models like GDD, SDD.
- Experience with STA constraints development and analysis for DFT modes and SDF simulations.
- Experience using EDA tools like Design Compiler, DFT Max, FastScan, TetraMax, Tessent, SpyGlass, Modus, Tessent, and TestKompress, VCS, NC-Verilog, and waveform debugging.
- Experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging ATPG patterns, Compressed ATPG patterns, MBIST and JTAG related issues.
- Knowledge of various test standards (such as IEEE 1149.10, 1149.6, 1500, 1687) and test formats (such as BSDL, ICL, PDL, STIL, CTL).
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Define DFX specifications and develop flows and methodologies for new technology node implementation.
- Implement/Integrate and verify DFT logic (e.g., memory built-in self test (MBIST), scan chains, DFT compression, TAP controller, BSCN, iJTAG instrumentation, functional BIST, logic BIST and eFuse logic on test chips).
- Work with the silicon engineering team to create test plans and generate test patterns.
- Participate in post-silicon activity like bring up, diagnostics, and characterization.
- Work with EDA and IP vendors to incorporate state-of-the-art DFT/DFD/DFY flows and methodologies. Provide support to internal teams.
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