ASIC Design Verification Engineer, TPU Compute
Job Summary
Job Description
- Bachelor's degree in CS/EE or equivalent
- 2+ years experience in ASIC verification
- SystemVerilog, SystemVerilog Assertions
- Functional coverage
- Plan verification, understand design specs
- Create constrained-random verification environment
- Master's/PhD in EE
- 6+ years experience in design verification
- UVM experience
- Industry-standard simulators, revision control, regression systems
- Full verification life cycle experience
- Bonus
- Equity
- Benefits
1 skill required
Job Details
Minimum qualifications:
- Bachelor's degree in Computer Science, Electrical Engineering, a related field, or equivalent practical experience.
- 2 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based Integrated Circuits (ICs) and chips.
- Experience with SystemVerilog (i.e., SystemVerilog Assertions or functional coverage).
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering.
- 6 years of experience in design verification.
- Experience with UVM (Universal Verification Methodology).
- Experience with industry-standard simulators, revision control systems and regression systems.
- Experienced with the full verification life cycle.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As an ASIC Design Verification Engineer, you will be part of a team developing ASICs used to accelerate computation in data centers. You will have responsibilities in areas such as project definition, design verification, and silicon bringup. You will participate in the architecture, documentation, and verification of the next generation of data center accelerators.
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about .
Responsibilities
- Plan the verification of digital design blocks, understand the design specification, and interact with design engineers to identify important verification scenarios.
- Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
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About The Company
A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.
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