This ASIC Engineer role involves designing custom silicon solutions for Google's direct-to-consumer products. Responsibilities include defining microarchitecture, performing RTL development in SystemVerilog, debugging simulations, conducting RTL quality checks (Lint, CDC, Synthesis, UPF), participating in synthesis, timing/power estimation, and FPGA/silicon bring-up. Collaboration with multi-disciplinary teams is crucial. The ideal candidate possesses expertise in RTL design using Verilog/System Verilog, microarchitecture, ARM-based SoCs, and ASIC methodology. Experience with low power estimation, timing closure, and synthesis methodologies is preferred.