ASIC Power Management Architect, Silicon

1 Week ago • 3 Years + • Research & Development

Job Summary

Job Description

This role involves defining ASIC power management architecture for ASICs to meet performance targets under power and thermal constraints. Responsibilities include algorithm development, modeling, and analysis of power management approaches, prototyping techniques at various design levels, and producing detailed documentation and trade-off analyses for reviews and product roadmap decisions. The ideal candidate will have experience in power management, ASIC power analysis, power components, modeling, power trees, and techniques like DVFS/AVS. Knowledge of PMICs, SMPS, LDO regulators, PDN, and the impact of software/architectural design on power and thermal behavior is also crucial. The position contributes to the development of custom silicon solutions for Google's direct-to-consumer products, pushing boundaries and shaping the future of hardware experiences.
Must have:
  • ASIC power management architecture definition
  • Algorithm development & power management analysis
  • Power management modeling & prototyping
  • 3+ years of experience in power management or design
Good to have:
  • Master's or PhD in relevant field
  • Experience with power components, modeling, and techniques like DVFS/AVS
  • Knowledge of PMICs, SMPS, LDOs, and PDN
  • Understanding of software/architectural impact on power and thermal behavior

Job Details


Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 3 years of experience in power management or power design/methodology.
  • Experience with ASIC power analysis methodology.

Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or equivalent practical experience.
  • Experience with power components, power modeling, power trees, and power management techniques such as Voltage Frequency Scaling (DVFS)/AVS, etc.
  • Experience with algorithmic development and prototyping for power management.
  • Knowledge of Power Management IC (PMIC), switched-mode power supply (SMPS) and low dropout (LDO) regulators, and power delivery network (PDN).
  • Knowledge of the impact of software and architectural design decisions on power and thermal behavior of the system, such as thermal mitigation and scheduling, and cross-layer policy design.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

  • Define ASIC power management architecture details for an ASIC to deliver exceptional performance under power and thermal constraints.
  • Perform algorithm development, modeling and analysis of power management approaches.
  • Model and prototype power management techniques applicable at different design levels.
  • Produce detailed documentation for the proposed implementation of power management schemes and produce detailed trade-off analysis for engineering reviews and product roadmap decisions.

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