ASIC RTL Design Engineer

As an ASIC RTL Design Engineer at Google, you'll be part of a team developing custom silicon solutions for Google's direct-to-consumer products. Responsibilities include RTL development using SystemVerilog, debugging simulations, performing RTL quality checks (Lint, CDC, Synthesis, UPF), participating in synthesis, timing/power estimation, and FPGA/silicon bring-up. You'll collaborate with multi-disciplinary teams across multiple locations. The role requires expertise in RTL design using Verilog/SystemVerilog, microarchitecture, scripting languages (Python/Perl), and experience with ARM-based SoCs, interconnects, and ASIC methodology. Preferred qualifications include a Master's degree, IP design experience, and knowledge of low-power estimation, timing closure, and synthesis methodologies.