CPU DFT Engineer

1 Month ago • 5-7 Years • Software Development & Engineering

Job Summary

Job Description

As a CPU DFT Engineer, you will be part of the P-Core design team, contributing to Intel's latest CPUs. Your responsibilities include DFT implementation for features like Scan, MBIST, and TAP. You will work on Spyglass DFT, RTL implementation, verification, Scan, and ATPG. The role requires strong knowledge of ATPG, fault models, memory BIST, and DFT logic generation. Experience with EDA tools and post-silicon support is a plus. You will be involved in design verification using standard simulators and post-silicon/ATE bring-up.
Must have:
  • Master's degree in Electronics or Computer Engineering.
  • 5+ years or 7+ years of DFT experience
  • Strong knowledge of ATPG and fault models.
  • Knowledge of memory BIST and IJTAG/TAP architecture.
Good to have:
  • Experience with manufacturing engineering and pattern delivery.
  • Experience with post-silicon support.
  • Experience in Design Verification (DV) using standard simulators e.g. VCS, Verdi waveform viewer

Job Details

Job Details:

Job Description: 

  • You will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology.
  • As a DFT engineer Direct Responsibilities of the role, but not limited to, working on various aspects of PCORE DFT including Spyglass DFT, RTL implementation, Verification, Scan, and ATPG.and nbsp.
  • The candidate must be able to drive the DFT implementation for various features incl Scan, MBIST, TAP, etc.
  • Previous experience working with manufacturing engineering, pattern delivery, and post-silicon support is a definite plus.

Qualifications:

  • Candidate must possess a master's degree in Electronics or Computer Engineering with at least 5 or more years of experience or a bachelor's degree with at least 7 years of experience of DFT experience.
  • Strong knowledge of ATPG, various fault models, fault grading Knowledge of memory BIST, IJTAG/TAP architecture DFT logic generation, integration, and verification EDA vendor-supported scan architectures and tools, covering synthesis, timing, DRC, ATPG, GLS (Unit delay and Timing/SDF based), and tester bring up preferably Mentor/Siemens Tessent Shell, TestKompress, ATPG coverage debug.
  • Experience in Design Verification (DV) using standard simulators e.g. VCS, Verdi waveform viewer Post Silicon/ATE Bring-Up Support Experience with RTL (Verilog, System Verilog, VHDL)

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Business group:

The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

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