CPU Frontend Design Engineer
Job Summary
Job Description
- Bachelor's degree in EE/CS or equivalent
- Full VLSI design cycle experience
- RTL implementation of low-power designs
- Verilog/SystemVerilog/VHDL experience
- Design verification, synthesis, timing/power analysis, DFT
- 4+ SoC cycles experience
- Knowledge of high-performance CPU architecture
- SVA experience
3 skills required
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
- Experience in full VLSI design cycle.
- Experience in RTL implementation of low power designs.
- Experience in VLSI development with Verilog, SystemVerilog, System Verilog Assertions (SVA), or VHDL, and with design verification, synthesis, timing/power analysis, and DFT.
Preferred qualifications:
- Experience in four or more SoC cycles.
- Knowledge of modern high-performance CPU architecture and micro-architecture.
About the job
As a CPU Frontend Design Engineer, you will take part in central processing unit (CPU) development, a complex and critical blocks of Google’s sever System on a Chip (SoC). You will be responsible for microarchitecture and RTL design and implementation of core technology as part of Google’s data center SoC products. You'll collaborate closely with architecture, verification, and physical design engineers, creating micro-architectural definitions with RTL coding and running block level simulations.
The ML, Systems & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
- Define architecture and micro-architecture features, write specifications, and understand implementation tradeoffs (e.g., performance, power, frequency, etc.).
- Define the CPU block level design document (e.g., interface protocol, block diagrams, transaction level flow, control registers, pipelines, etc.).
- Perform RTL development process (e.g., coding and debug in Verilog, SystemVerilog, or VHDL), function/performance simulation debug, and Lint/CDC/FeV/PowerIntent checks.
- Contribute to the SoC level integration, and participate in synthesis, timing/power closure, and silicon bring-up.
- Participate in test plan and coverage analysis of the block and SoC-level verification.
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