Job Description:

Cadence/Tensilica is a leading provider of configurable embedded processor technology and DSPs for various markets. As a member of the DSP engineering group you will be responsible for verification of advanced DSP cores and their instruction set architectures and hardware implementations. You will implement architectural simulation testbenches in C/C++/RTL, write C/assembly language diagnostics, assertion checkers or coverage monitors to meet target verification goals. You will also assist with developing test plans, debugging failures and analyzing coverage information. You will work closely with the market-specific DSP teams, Design Verification, and RTL and EDA teams.

Qualifications:

1) Knowledge of DSPs, instructions sets, computer arithmetic concepts, and processor architecture concepts

2) Good knowledge of C (C++ will be a plus)

3) Working knowledge of Verilog and popular EDA simulators and testbench methodologies

4) Knowledge of scripting languages such as Makefile/Perl is desired

5) Knowledge of assembly programming and programming in a high level language such as C will be a plus

6) Good English communication skills - both written and verbal

7) Strong problem solving skills along with an ability to work independently and in cooperation with global teams.