Design Verification Engineer
Job Description
- MIPI knowledge
- Video IPs (ISP/Encoder/Decoder) knowledge
- 2-4 years experience
- System Verilog & OVM/UVM
- AXI/AHB/APB/ACE5 bus knowledge
- Waveform debug skills (VCS, NCSIM, Verdi, ModelSim)
- Testbench development
- Coverage & assertions
- Scripting (Perl/Tcl/Python)
- Cross-functional teamwork
Project description
Join our team in developing cutting-edge technology. This role demands a high level of expertise in Testing. The ideal candidate has a background in SW engineering, data structures, verification processes, with
strong fundamentals in scripting language and Verilog. The candidate should have a fair understanding
of SW quality and processes.
Responsibilities
The candidate will be responsible for design, development and
maintenance, of clients device model verification tools. We are looking for smart, creative people who have a passion for solving challenging problems.
Skills
Must have
Candidate should have 2-4 years' experience
Strong Familiarity with System Verilog and OVM/UVM Verification Methodology
Knowledge of system-level architecture including buses like AXI/AHB/APB/ACE5
Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM, Verdi, ModelSim
Ability to work with cross-functional teams
Proficiency in developing the TB environment
Good Knowledge on writing coverage and assertions
Good knowledge in scripting(Perl/Tcl/Python) and automation of verification flows/process
Knowledge of mipi, video Ips like ISP/Encoder/Decoder would be useful
Nice to have
Education : B.Tech/M.Tech ECE
Other
Languages
English: B2 Upper Intermediate
Seniority
Regular
