Design Verification Engineer

Meta's Reality Labs(RL) focuses on delivering Meta's vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. Meta RL Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital design and verifications skills to implement the testing infrastructure to validate new core IP implementations and contribute to development and optimization of state of the art vision and sensing algorithms. You will work closely with researchers, architects and designers in creating test bench requirements and test cases for multiple state of the art IPs. Responsibilities: Work with researchers and architects defining verification plans for each of the different core IP. Define and track detailed test plans for the different modules and top levels. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage. Debug, root-cause and resolve functional failures in the design, partnering with the Design team. Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality. Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.