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Design Verification Engineer

Design Verification Engineer

1 Month ago • 5-5 Years • Research & Development

About the job

12 skills required for this role

Test your skills to join the top 1% applicants for this job

shell

unity

cpp

algorithms

github

computer-vision

python

perl

svn

git

networking

cross-functional

Job Description

Meta's Reality Labs (RL) focuses on delivering Meta's vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. Meta RL Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital design and verifications skills to implement the testing infrastructure to validate new core IP implementations and contribute to development and optimization of state of the art vision and sensing algorithms. You will work closely with researchers, architects and designers in creating test bench requirements and test cases for multiple state of the art IPs.

Must have:

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
Track record of 'first-pass success' in ASIC development cycles.
5+ years of hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology.
5+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies.
Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation.
Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.
Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle.

Good to have:

Experience in development of UVM based verification environments from scratch.
Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs.
Experience with revision control systems like Mercurial(Hg), Git or SVN.
Experience with low power design.
Experience working across and building relationships with cross-functional design, model and emulation teams.

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Meta's Reality Labs(RL) focuses on delivering Meta's vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. Meta RL Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital design and verifications skills to implement the testing infrastructure to validate new core IP implementations and contribute to development and optimization of state of the art vision and sensing algorithms. You will work closely with researchers, architects and designers in creating test bench requirements and test cases for multiple state of the art IPs.

Design Verification Engineer Responsibilities

Work with researchers and architects defining verification plans for each of the different core IP.

Define and track detailed test plans for the different modules and top levels.

Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.

Debug, root-cause and resolve functional failures in the design, partnering with the Design team.

Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.

Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.

Minimum Qualifications

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.

Track record of 'first-pass success' in ASIC development cycles.

5+ years of hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology.

5+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies.

Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation.

Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.

Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle.

Preferred Qualifications

Experience in development of UVM based verification environments from scratch.

Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs.

Experience with revision control systems like Mercurial(Hg), Git or SVN.

Experience with low power design.

Experience working across and building relationships with cross-functional design, model and emulation teams.

For those who live in or expect to work from California if hired for this position, please click for additional information.

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Locations

Data Center

About Meta

Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.

$142,000/year to $203,000/year + bonus + equity + benefits

Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about at Meta.

Equal Employment Opportunity and Affirmative Action

Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. You may view our Equal Employment Opportunity notice .

Meta is committed to providing reasonable support (called accommodations) in our recruiting processes for candidates with disabilities, long term conditions, mental health conditions or sincerely held religious beliefs, or who are neurodivergent or require pregnancy-related support. If you need support, please reach out to .

View Full Job Description

$142.0K - $203.0K/yr (Outscal est.)

$172.5K/yr avg.

Sunnyvale, California, United States

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