Design Verification Senior Principal Engineer

1 Month ago • 8-15 Years

About the job

SummaryBy Outscal

Marvell seeks a Senior Principal Design Verification Engineer with 8+ years of experience in UVM, Verilog/SystemVerilog, and scripting languages like Perl, Tcl, or Python. The ideal candidate possesses strong networking knowledge and excellent communication skills.

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

The Switch Business Unit in Marvell designs and develops the next generation datacenter and enterprise System-On-Chip switch processors on leading edge process technology. We develop the architecture, collaborate on IP development, create the physical design, develop switching solutions and work with the world’s leading data center and enterprise companies to bring next generation networking to reality.

What You Can Expect

  • Develop and maintain verification environment in UVM (Universal Verification Methodology)
  • Define and review verification test plan with architecture team and design team
  • Verify the design with directed and constraint random functional parameters
  • Maintain regression and debug test failures with designers
  • Report and analyze verification coverage of design features and parameters
  • Drive the verification to reach coverage target
  • Take responsibility in the verification of blocks, sub-systems and top-level environment.

What We're Looking For

  • Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 8-15 years of related professional experience.
  • Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.
  • Hands-on experience on using Verilog, System Verilog and UVM (Universal Verification Methodology)
  • Good scripting skills in languages such as Perl, Tcl, or Python.
  • Experience in networking domain is a plus.
  • Good verbal and written communication skills in English.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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