Design Verification Senior Staff Engineer
Job Description
- Responsible for functional verification of co-processor sub-system units.
- Handle features like pcie/ethernet packet processing, offload protocol engines, cryptography, processor scheduling, traffic management, machine learning.
- Develop and execute verification plans using random techniques and coverage analysis.
- Create and maintain testbenches and test cases.
- Perform functional and performance verification.
- Debug and resolve design and verification issues.
- Collaborate with design and architecture teams to ensure verification coverage.
- Possess excellent problem-solving and analytical skills.
- Demonstrate strong communication and teamwork abilities.
- Ability to mentor junior engineers and lead verification projects.
- Bachelor’s degree in Computer Science, Electrical Engineering, or related fields with 4+ years of experience.
- Master’s degree or PhD in Computer Science, Electrical Engineering or related fields with 3+ years of experience.
- Proficiency in SystemVerilog and UVM.
- Experience with simulation tools (e.g., VCS).
- Knowledge of scripting languages (Python, Perl, TCL).
- flexible time off
- 401k
- year-end shutdown
- floating holidays
- paid time off to volunteer
Your Team, Your Impact
Custom Compute & Storage (CCS) Business Unit, is one of Marvell's fastest growing business units. In CCS, we focus on helping our customers with their custom designs for cloud-based AI applications as well as customers in the enterprise and carrier markets. As a member of the verification team, the candidate will be responsible for functional verification of one or more units that make up the co-processor sub-system. Handling such features as pcie/ethernet packet processing, offload protocol engines, cryptography, processor scheduling, traffic management, machine learning, etc.
What You Can Expect
- Develop and execute verification plans using random techniques and coverage analysis.
- Create and maintain testbenches and test cases.
- Perform functional and performance verification.
- Debug and resolve design and verification issues.
- Collaborate with design and architecture teams to ensure verification coverage.
- Excellent problem-solving and analytical skills.
- Strong communication and teamwork abilities.
- Ability to mentor junior engineers and lead verification projects.
What We're Looking For
- Bachelor’s degree in Computer Science, Electrical Engineering, or related fields and 4+ years of related professional experience.
- Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3+ years of experience.
- Proficiency in SystemVerilog and UVM (Universal Verification Methodology).
- Experience with simulation tools (e.g., VCS) and knowledge of scripting languages (Python, Perl, TCL).
Expected Base Pay Range (USD)
139,800 - 206,900, $ per annum
The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
