This role involves developing and deploying tools and infrastructure to enhance the productivity of Google's CPU design verification team. Responsibilities include managing large-scale regression flows for simulation, emulation, and FPGA platforms, including automated test generation. The position requires developing and utilizing databases for verification metrics and evaluating/integrating EDA tools into verification flows. Continuous improvement of verification flows is a key objective. The ideal candidate will have experience with verification flow infrastructure, CAD, Python/Perl scripting, and simulation tools like Cadence IES/Xcelium, Synopsys VCS, or Mentor Questa. Experience with EDA tools, emulation/FPGA, databases (SQL/Oracle), and interfacing with CAD/IT teams is preferred. This is a full-time position with a competitive salary and benefits package.