EDA Tools Hardware Engineer

Job Description

Do Something Wonderful!

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Want to learn more? Visit our or the links below! 

Who We Are

This role is part of a central Design for Test (DFT) methodology team that supports the majority of Intel's IP and SOC teams. We provide DFT architectures, IPs, tools, and workflows tailored to meet the requirements of Intel's designs.

Who You Are

Responsibilities include but not limited to:

• Designs, implements, verifies, and supports the enablement and adoption of hardware design tools, flows, and methodologies.

• Defines methodologies for hardware development related to technology node and EDA tool enabling.

• Creates and verifies unique hardware designs, assembles design platforms, and integrates components into hierarchical systems to provide deployment coverage for end-to-end EDA tool testing on new technology nodes.

• Develops, tests, and analyzes engineering design automation tools, flow, and methodologies to improve efficiency and optimize power and performance.

• Supports development and enhancement of platforms, databases, scripts, and tools flows for design automation.

• Builds deep understanding of digital design, verification, structural and physical layout, full chip integration, power and performance, clocking, and/or timing to enhance future TFM development.

• Collaborates with EDA vendors on defining and early testing of next generation design tools.

Preferred Qualifications:

• Programming skills with one or more of the high-level languages e.g. Verilog/C/C++/TCL/Perl/Python.

• Standard software engineering practices for version control, configuration management, debugging and validation.

Join us at Intel and become a driving force behind the mechanical and thermal solutions shaping tomorrow's innovations.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering or any similar STEM degree with 6+ years of relevant experience, OR Master's degree with 4+ years of relevant experience.

xperience should include the following:

• Logic and memory design principles, VLSI design flow and VLSI CAD algorithms.

• Tool, flows and methodology development for DFT insertion and test generation needs.

• DFT validation methodology using Verilog and EDA testbench

Inside this Business Group

Product Enablement Solutions Group (PESG) is one of the key pillars, enabling Intel product design teams get to market faster with winning leadership products.

Other Locations

US, OR, Hillsboro; US, CA, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits Annual Salary Range for jobs which could be performed in the US $144,501.00-$217,311.00*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.