Full Chip CAD Physical Design Verification Engineer

As a Full Chip CAD Physical Design Verification Engineer at Google, you'll be a key part of a diverse team pushing the boundaries of custom silicon solutions for Google's direct-to-consumer products. You'll directly contribute to the innovation behind products used by millions worldwide, shaping the next generation of hardware experiences. You'll bring expertise in Register-Transfer Level (RTL)-to-Graphic Data Stream (GDS)II flow, Cadence design tools, and the implementation of large, complex system-on-chips (SoCs), subsystems, and sub-wrappers. Your skills in floorplanning, power grid design, place-and-route methodologies, and Synopsis tools like Floorplan Compiler (FC) and formality will be essential. Understanding advanced node design and related optimization techniques, as well as expertise in scripting languages like Synopsis TCL and Python are crucial. This role offers a unique opportunity to contribute to the cutting edge of hardware development at one of the world's leading technology companies.