IC Design Engineer

The Central Engineering Team is responsible for standard cell development and custom design solutions that power cutting-edge AI compute cores and CPUs. We are seeking a motivated and technically strong engineer to join our team.

Job Description:

• Leading STA efforts in complex compute blocks
• Will be responsible for defining/ co-defining timing constraints with the customer and interface with the physical design team
• Responsible to drive state of the art in timing closure
• Participate/contribute in silicon bring-up, characterization, and silicon test
• Participate in timing closure of the blocks with best PPA (power/performance/area)

Ideal Candidate Will Have:

• The candidate should have a strong understanding of VLSI and ASIC physical design
• Significant experience with synthesis and physical synthesis tools (Synopsys and Cadence tool suites preferred)
• Deep understanding of PLLs and clock networks
• Significant experience using a static timing analysis tool. Preferably Synopsys PrimeTime and/or Cadence Tempus.
• - Ability to create and debug timing constraints
• - Ability to understand and debug warning and error messages from the timing tool
• - Ability to generate and understand timing reports
• Deep understanding of STA concepts
• - Solid understanding of RC networks and how they affect the timing/propagation of signals
• - Understanding of Signal Integrity, Crosstalk Delay, and Glitch/Noise Analysis
• - Understanding of setup analysis, hold analysis, and other timing checks
• - Ability to understand and create timing diagrams
• Deep understanding of more advanced STA concepts
• - POCV/SOCV/LVF modeling of variation
• - MIS - multi input switching
• - CCS/ECSM/NLDM - liberty timing models
• - PBA - path based analysis
• - LOCV/SOCV - location aware timing derates
• Experience using SPICE analysis
• Master’s degree in Engineering with 10+ years of hands-on experience in Place and route tools, or PhD (preferred) with 7+ years of experience.

Join us in shaping the next generation of high-performance compute technologies.

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $141,300 - $226,000

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.