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Interposer Physical Design Engineer

Interposer Physical Design Engineer

3 Weeks ago • 10 Years + • Research & Development

About the job

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Job Description

This role involves owning interposer routing for 2.5D or 3D packaging, including custom signal routing, shielding, and power/ground distribution. Responsibilities include connecting general-purpose and high-speed interfaces, performing ASIC top-level I/O planning and RDL routing, and conducting technical evaluations of interposers and advanced packaging. Collaboration with ASIC designers, package designers, and system architects is crucial for defining layout and specification requirements. The ideal candidate will have 10+ years of experience in ASIC physical design flows, experience with various interconnect technologies (C4 bumps, micro bumps, TSVs, etc.), and proficiency in industry-standard physical verification and analysis tools. The position requires expertise in high-speed signal integrity and design for manufacturability (DFM).

Must have:

10+ years ASIC physical design experience
Advanced process node expertise
Custom routing and PnR tool experience
Physical verification and DFM knowledge
Interposer routing and high-speed signal integrity
Collaboration with cross-functional teams

Good to have:

Interposer or package design leadership
QoR metrics extraction and analysis
Interposer design testing and debugging
Semiconductor device physics knowledge
Thermal considerations for 3D stacked dies

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Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience in ASIC physical design flows and methodologies in advanced process nodes.
Experience with routing through custom routing or PnR tool routing.
Experience with layout, physical verification, Design for Manufacturability (DFM), power and signal integrity analysis using industry standard tools.
Experience with Controlled-Collapse Chip Connection (C4) bumps, micro bumps, Deep Trench Capacitor (DTC), Through-silicon via (TSV) etc.

Preferred qualifications:

Experience with leading one or more aspects of interposer or package design.
Experience in extraction of design parameters, Quality of Results (QoR) metrics, and analyzing trends.
Knowledge of techniques for testing and debugging interposer designs, including electrical and thermal.
Knowledge of semiconductor device physics and transistor characteristics.
Understanding of thermal considerations for 3D stacked dies and interposers.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $177,000-$266,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about .

Responsibilities

Own interposer routing necessary for 2.5D or 3D packaging (i.e., custom signal routing, shielding and power/ground distribution).
Connect general purpose and high speed interfaces through an interposer with consideration for high speed effects, signal integrity, etc.
Perform Application-Specific Integrated Circuit (ASIC) top level I/O planning and Redistribution Layer (RDL) routing.
Perform technical evaluations of interposers, advanced packaging, process nodes, IP and provide recommendations.
Collaborate with other design teams, including ASIC designers, package designers, and system architects on interposer layout and specification requirements, collaterals, and milestone timelines.

View Full Job Description

$177.0K - $266.0K/yr (Outscal est.)

$221.5K/yr avg.

Worldwide

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About The Company

Google

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A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.