IO Validation Methodology Design Engineer

NVIDIA's GPUs and SOCs are the world leaders in performance and efficiency, and we are continually innovating in creative and unique ways to improve our ability to deliver extraordinary solutions in a wide range of sectors. We are seeking versatile engineers who are passionate about what they do and are committed to making a difference in the world through their inventions. 

NVIDIA Silicon Solutions Group is seeking a versatile engineer to be part of the HW ArchDev team. You will dive into HSIO(High Speed IO -CXL/COU etc) and LSIO(Low Speed IO - I2C/I3C/QSPI/SPI/UART etc) to make advancements in efficiency and stability for our GPU and SOC product. The SSG team is uniquely positioned to have an end-to-end view of the product development cycle - from early arch definition through bringup to product release. Our ArchDev arm is a hub for all silicon and system-level feature development, tradeoff analysis, system integration solutions, system POR alignment and system bringup, validation, debug and tuning. 

What You'll Be Doing: 

• Proactively dive into new feature and spec from Pre-Si and lead test strategies development, including functional validation strategy, characterization and tuning methodology, platform/component interoperability, test design, debug capability and tools/scripts, system, SLT, and manufacturing test requirement. 

• Lead IO new feature silicon bring-up, validation, and debug, and coordinate product schedule to release feature with high quality at aggressive schedule. 

• Deep dive into technically challenging IO Pre-Si and Post-Si bugs and lead  debug efforts across various teams (ASIC/FW/SW/PHY/board) to fix the issue on schedule and envision design optimization and collaborate with designer to implement for next generation. 

• Proactively drive and identify opportunities and methods for test strategies and validation methodology optimization, efficiency improvement and innovation based on project learnings and challengings.

What We Need To See: 

• BS or MS degree in EE/CE or equivalent experience.

• 5+ years in silicon system architecture, digital design, validation, and debugging in HSIO, LSIO, PLL, Clocking and SerDes related areas.

• Depth in one or more areas of high-performance circuit SerDes and high-speed and Low-speed signaling, photonics, SRAMs, power delivery/regulation, security circuits, and high-speed logic).

• Strong understanding on protocol spec in HSIO (PCIE, CXL, USB) and LSIO (SPI/I2C/I3C/UART).

• Experiences on Power management and performance/power optimization, validation etc.

• Strong EE fundamentals, knowledgeable in digital design, computer architecture, power analysis, timing analysis, fault analysis, sampling, statistics, and scripting.

• Excellent verbal communication and written, presentation skills.

• Deep understanding of firmware/driver structures and their interaction with HW.

• Working knowledge of PVT dependencies and binning methodologies.

• Experience with Python/perf etc script development, Windows and Linux OS is a plus.

• Effective in a collaborative environment.

With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world’s most desirable employers. We welcome you join our team with some of the most hard-working people in the world working together to promote rapid growth. Are you passionate about becoming a part of a best-in-class team supporting the latest in GPU and AI technology? If so, we want to hear from you.