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Lead CPU RTL Engineer, Silicon

New York, United States (On-site)

Lead CPU RTL Engineer, Silicon

1 Hour ago • 8 Years + • Research & Development

About the job

2 skills required for this role

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algorithms

innovation

Job Description

Lead CPU RTL Engineer at Google will contribute to CPU frontend designs, focusing on microarchitecture and RTL design for next-generation CPUs. Responsibilities include proposing performance-enhancing microarchitecture features, collaborating with architects and performance teams on trade-off studies, and delivering designs meeting Power, Performance, and Area (PPA) goals. The role requires expertise in digital logic design, RTL design (Verilog/SystemVerilog), logic synthesis, and low-power design techniques. Experience with modern processor microarchitecture is preferred. The successful candidate will become familiar with state-of-the-art techniques for at least one processor functional block and contribute to performance modeling. The position is located in Poughkeepsie, NY, or Austin, TX.

Must have:

8+ years of experience in digital logic design
RTL design expertise (Verilog/SystemVerilog)
Logic synthesis and low-power design techniques
Contribute to CPU frontend designs
Propose performance-enhancing microarchitecture features

Good to have:

Master's or PhD in relevant field
Experience with modern processor microarchitecture
Experience with performance modeling

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.

Preferred qualifications:

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with modern processor micro-architecture and related technologies and algorithms.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $177,000-$266,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about .

Responsibilities

Contribute to CPU frontend designs, emphasizing on microarchitecture and RTL design for the next generation CPU.
Propose performance enhancing microarchitecture features with efficiency in mind. Work with architects and performance teams for trade-off studies. Communicate pros and cons of microarchitecture enhancements. Facilitate final decision making.
Deliver designs meeting Power, performance and area (PPA) goals with production quality.
Become familiar with state-of-the-art techniques for at least one processor functional block. Interpret the techniques into design constructs and languages in order to provide guidance to and participate in the performance modeling effort.

View Full Job Description

$177.0K - $266.0K/yr (Outscal est.)

$221.5K/yr avg.

Poughkeepsie, New York, United States

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About The Company

Google

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A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.