Lead Design Engineer

About the job

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title: Lead Design Engineer (Lead Design Verification Engineer)

Location: Bangalore

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success.
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests.
• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.
  
  

Job Summary

Cadence is seeking an experienced design verification engineer who will play a critical role in the development of custom accelerator SoCs, in partnership with Cadence computational simulation teams.

Job Responsibilities: (Design Verification Engineer)

• The qualified candidate will closely work together with ARCH, RTL and FW/SW team in implementation and optimization of our accelerator solution.
• The candidate must possess hands-on experience and excellent debugging skills in developing System Verilog/UVM based testbenches.
• Ability to independently verify complex modules in the context of subsystem/SOC using systemic metric-driven approach must be demonstrated.
• Past participation in successful IP delivery or SOC tape-out is highly desired.
• Effective cross-team communication and documentation skill is strongly preferred.
• Experience in automating verification regression and/or management of revision control is a plus.
  
  

Qualifications

Minimal qualification requires BS/MS degree ECE or CS with 4+ years of experience in Design verification.

Behavioral Skills Required

• Must possess strong written, verbal and presentation skills.
• Ability to establish a close working relationship with both customer peers and management.
• Explore what’s possible to get the job done, including creative use of unconventional solutions.
• Work effectively across functions and geographies.
• Push to raise the bar while always operating with integrity.
  
  

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