Lead Systems Engineer -High Speed Interconnect IPs.

7 Months ago • 3 Years + • Research & Development • $131,600 PA - $244,400 PA

Job Summary

Job Description

Lead Systems Engineer for high-speed interconnect IPs. Develop best-in-class digital and mixed signal IP. Must have strong communication skills, ability to manage multiple priorities, and ownership of tasks. Experience in analog design and advanced process technologies is required.
Must have:
  • Analog Design
  • Advanced Process
  • Communication Skills
  • Multiple Priorities
Good to have:
  • Serial Link
  • Data Converter
  • Clock Synthesis
  • MATLAB or C
Perks:
  • Employee Stock
  • Medical Benefits

Job Details

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

  

Join a growing and dynamic IP team and help lead the development of best in class digital and mixed signal IP and subsystem products.  This is a tremendous opportunity to work with an experienced team focusing on development of high-performance silicon subsystems   integrating Controller and PHY  IPs related to protocols such as PCIe/CXL, UCIe , Ethernet…. 

You will be a key member of technical staff in an organization responsible for IP activities including but not limited to developing sub system prototypes in hardware and software, Help Product marketing team in sub system solutions launch, Pre-sales technical engagement with potential customers. This candidate will be the primary interface between customers (internal and external) customers CDNS R&D/ Silicon Systems validation team. Candidate should possess strong communication skills with ability to manage multiple priorities on day-to-day basis. Ownership of tasks, ability to collaborate with remote teams located worldwide and clear communication of status, are must have attributes in this role. 

Familiarity with the following items is a plus:

  • Serial link design techniques
  • Data converter (ADCs and/or DACs) and/or clock synthesis and recovery (PLLs, DLLs, CDRs) techniques
  • MATLAB or C to facilitate architecture development
  • Hardware description languages such as SystemVerilog or VerilogA for functional model development
  • Scripting languages such as Perl or Python for automation
  • Silicon validation testing knowledge and experience

Other requirements:

  • Excellent verbal and written communication skills
  • Mid-senior level- Senior level
  • MS/Ph.D. EE degree with 3+ years of analog design industry experience in advanced process technologies

The annual salary range for California is $131,600 to $244,400. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

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