Networking SoC Architect, Google Cloud

1 Month ago • 8 Years + • Research & Development

About the job

Job Description

This role involves designing and architecting custom silicon solutions for Google's data center networking. Responsibilities include evaluating silicon solutions (off-the-shelf, co-developments, custom designs), creating high-performance hardware/software interfaces, and collaborating with various teams (software, verification, etc.) to ensure design correctness and performance. The architect will also drive vendor execution and participate in evaluating future ASIC designs. The ideal candidate possesses deep understanding of RDMA, packet processors, networking protocols (TCP/IP, Ethernet, PCIe), and micro-architecture design. They will perform performance analysis of the end-to-end networking stack and define performance test plans.
Must have:
  • 8+ years network architecture experience
  • RTL ASIC subsystem development
  • Micro-architecture, design, verification expertise
  • RDMA or packet processor IP architecture experience
  • Collaboration with software teams
Good to have:
  • Experience with networking switches, endpoints, hardware offloads
  • Proficiency in C++, Python, or Go
  • Deep understanding of packet processing, queueing, switching, routing
  • Performance estimation and test plan definition

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 8 years of experience working in network architecture and system design principles for low latency, high throughput, security, and reliability.
  • Experience developing RTL for ASIC subsystems.
  • Experience in micro-architecture, design, verification, logic synthesis, and timing closure.
  • Experience in architecting RDMA or packet processor IPs across multiple generations.

Preferred qualifications:

  • Experience architecting networking switches, end points, and hardware offloads.
  • Experience with TCP, IP, Ethernet, PCIE, and DRAM, and familiarity with Network on Chip (NoC) principles and protocols (e.g., AXI, ACE, and CHI).
  • Experience working with software teams optimizing the hardware/software interface.
  • Proficiency in a procedural programming language (e.g., C++, Python, Go).
  • Deep understanding of packet classification, processing, queueing, scheduling, switching, routing, traffic conditioning, and telemetry.
  • Ability to estimate performance by analysis, modeling, and network simulation, and define and drive performance test plans.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will be part of a team defining solutions for network accelerations in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, with close collaborations with software teams. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators. You will be responsible for performance analysis for an end to end networking stack using your deep knowledge of RDMA and packet processors based transports.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

  • Evaluate different silicon solutions for executing Google’s data center networking roadmap: off-the-shelf components, vendor co-developments, custom designs, and chiplets.
  • Create high performance hardware/software interfaces.
  • Collaborate closely with software, verification, emulation, physical design, packaging, and silicon validation stakeholders to ensure that designs are complete, correct, and performant.
  • Drive vendor execution in various engagements: standard component roadmaps, build to specification, and co-developments.
  • Participate in evaluation of future ASIC designs and general architecture.
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About The Company

A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.

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