Ph.D. Candidate - Development of high-level fault models for validation of AI accelerators - Contract Duration 3 Years (f/m/d)

4 Months ago • All levels • Research & Development

Job Summary

Job Description

Job Details

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

In recent years, the adoption of Artificial Intelligence (AI) at the edge, particularly in the automotive industry, has surged dramatically. Edge AI, crucial for Advanced Driver Assistance Systems (ADAS), enables real-time hazard detection and significantly enhances driver safety. AI accelerators, which provide the computational power for these critical applications, are becoming deeply integrated into automotive systems. As their role expands, ensuring their safety and reliability through advanced fault models and safety verification techniques is vital. In addition, tailored Electronic Design Automation (EDA) methodologies are essential for developing AI accelerators that comply with the stringent safety standards required in the automotive industry.

This Ph.D. research focuses on developing advanced fault models and safety verification techniques for AI accelerators using cutting-edge EDA tools. The research will involve exploring safety analysis methodologies using functional testing techniques or metric-driven verification methodologies tailored to AI accelerators. Additionally, the project will exploit and optimize safety verification techniques, such as simulation-based fault injection and formal verification, to enhance the safety of AI accelerators. The solutions developed will be integrated into the overall Cadence Functional Safety tool flow, resulting in an advanced methodology that improves safety verification processes and accelerates the time-to-market for AI accelerator design.

Specific background:

  • M.Sc. (or equivalent) in Electrical Engineering, Computer Engineering, Computer Science, or related areas
  • Understanding of digital integrated circuit digital design & verification flows and tools
  • Knowledge of hardware design languages (Verilog, VHDL) and programming skills
  • Theoretical background in Functional Safety is preferred.

Requirements:

Note: This Ph.D. project is part of the TIRAMISU European HORIZON MSCA Doctoral Network. The application for DC2.4 must also be submitted via the TIRAMISU website: https://tiramisu-project.eu/vacancies/application-procedure

Benefits we offer you:

  • Competitive Salary
  • 30 days annual leave
  • Meal vouchers
  • Capital Forming Payment (VwL)
  • Ticket for the public transport
  • Working in a hybrid model in a modern office concept

And so much more, do not hesitate to contact us.

We’re doing work that matters. Help us solve what others can’t.

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