Physical Design Engineer

6 Months ago • 2 Years + • Software Development & Engineering

Job Summary

Job Description

NVIDIA's Shanghai team seeks a Physical Design Engineer to contribute to the design of GPUs and mobile chips. Responsibilities encompass full chip floorplanning, power/clock distribution, timing optimization, place & route, timing closure, power/signal integrity analysis, and physical verification. The role involves troubleshooting design and flow issues, collaborating with RTL, DFT, and circuit designers, and utilizing advanced EDA tools like Synopsys (ICC2/FC/PT/STAR-RC) and Cadence (EDI/Innovus/Voltus). The ideal candidate possesses 2+ years of experience in physical design on advanced technology nodes and a strong understanding of clock/power distribution, P&R, and timing closure.
Must have:
  • BS in Engineering or Science
  • Power user of Synopsys & Cadence EDA tools
  • Experience in Clock/Power Distribution, P&R, Timing Closure
  • Experience on advanced technology nodes
  • Physical verification experience
Good to have:
  • MS in Engineering or Science
  • FinFET technology knowledge
  • Experience with Synopsys ICV or Mentor Calibre
  • Proficiency in Perl, Python, TCL, and Makefile scripts

Job Details

We are now looking for a Physical Design Engineer. VLSI Physical Design Team at NVIDIA Shanghai has been built up since 2005. The team has made contribution to various successful products launched by NVIDIA Corporation over 15 years. We utilize latest process technology, advanced EDA tools, and sophisticated design methodology. We always work on the most challenging designs, and push for performance limit.

What you’ll be doing:

  • A role in physical design for NVIDIA GPU and Mobile chips.

  • Participate in various aspects of physical design, including full chip floorplanning, power/clock distribution, timing optimization, place & route, timing closure, power/signal integrity analysis, and physical verification.

  • Troubleshoot a wide variety of design and flow complicated issues, and apply proactive intervention Collaborate with RTL, DFT and Circuit designers to ensure high quality of design implementation.

What we need to see: 

  • BS in Engineering or Science or equivalent experience.

  • Power user of EDA tools from Synopsys (ICC2/FC/PT/STAR-RC), Cadence (EDI/Innovus/Voltus).

  • Experience in Clock/Power Distribution, P&R, Timing closure, RC Extraction, and verification on advanced technology nodes.

  • 2+ years of experience in above areas.

Ways to stand out from the crowd:

  • MS in Engineering or Science.

  • Knowledge in FinFET technology, circuit design, and package design.

  • Experience in physical verification tools from Synopsys (ICV) or Mentor (Calibre).

  • Proficiency in Perl, Python, TCL and Makefile scripts.

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About The Company

Since its founding in 1993, NVIDIA (NASDAQ: NVDA) has been a pioneer in accelerated computing. The company’s invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined computer graphics, ignited the era of modern AI and is fueling the creation of the metaverse. NVIDIA is now a full-stack computing company with data-center-scale offerings that are reshaping industry.

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