Physical Design Engineer

9 Hours ago • 2-4 Years

Job Summary

Job Description

As a Physical Design Engineer at Qualcomm, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems. You will work on high-speed core designs and ensure proper timing signoff. Responsibilities include leading block or chip-level Physical Design, STA, and PDN activities, implementing RTL to GDSII, collaborating to resolve issues, and utilizing low power flow knowledge. The role requires strong problem-solving skills and the ability to handle technical deliveries.

Must have:

Experience in Physical Design and timing signoff for high speed cores.
Good exposure to high frequency design convergence with PPA targets.
Experience in IC design with at least 7+ years of experience.
Experience in leading block or chip level Physical Design, STA, and PDN.
Work independently in the areas of RTL to GDSII implementation.
Knowledge of low power flow (power gating, multi-Vt flow, etc.).
Circuit level comprehension of time critical paths in the design
Tcl/Perl scripting and willingness to handle technical deliveries.

3 skills required

3 skills required for this role

Add these skills to join the top 1% applicants for this job

perl

fpga

cross-functional

Job Details

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

2-4 yrs experience in Physical Design and timing signoff for high speed cores.
Should have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology.
Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 7+ years of experience in IC design.
Experience in leading block level or chip level Physical Design, STA and PDN activities.
Work independently in the areas of RTL to GDSII implementation.
Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc.
Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.)
Circuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.)
Tcl/Perl scripting Willing to handle technical deliveries with a small team of engineers.
Strong problem-solving skills.

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