Physical Design Engineer, Silicon, Google Cloud

3 Months ago • 4 Years + • Research & Development

Job Summary

Job Description

Google Cloud seeks a Physical Design Engineer to contribute to the development of custom silicon solutions for direct-to-consumer products. The role involves designing cutting-edge ASICs to accelerate machine learning in data centers. Responsibilities include defining and implementing physical design methodologies, taking ownership of design partitions, ensuring timing and power closure, contributing to design methodologies and code reviews, and defining rule sets for functional design engineers. Collaboration with architecture, verification, and power teams is crucial. The ideal candidate possesses expertise in advanced design, DFT, low-power design, and SoC cycles, with experience in System Verilog and TCL scripting preferred.
Must have:
  • Bachelor's degree in EE or equivalent
  • 4+ years experience in advanced design
  • SoC cycle experience
  • Experience with clock/voltage domain crossing
  • DFT and low power design expertise
Good to have:
  • Master's degree in EE
  • System Verilog and TCL scripting
  • Multiple SoC cycles in ASIC design
  • Layout verification and design rule experience
  • VLSI design in SoC

Job Details

Minimum qualifications:

  • Bachelor’s degree in Electrical Engineering or equivalent practical experience.
  • 4 years of experience with advanced design, including clock/voltage domain crossing, Design for Testing (DFT), and low power designs.
  • Experience with System on a Chip (SoC) cycles.
  • Experience with performance, frequency, and low-power designs.

Preferred qualifications:

  • Master’s degree in Electrical Engineering, or a related field.
  • Experience coding with System Verilog and scripting with TCL.
  • Experience with multiple cycles of SoC in ASIC design.
  • Experience with layout verification and design rules.
  • Experience with VLSI design in SoC.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

You will be part of a team developing a cutting-edge Application-specific integrated circuit (ASIC) used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design etc. to specify and deliver high quality designs for next generation data center accelerators. You'll solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

  • Define and drive to the implementation of physical design methodologies.
  • Take ownership of one or more physical design partitions or top-level.
  • Drive to the closure of timing and power consumption of the design.
  • Contribute to design methodology, libraries, and code review.
  • Define the physical design related rule sets for the functional design engineers.

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