Principal Application Engineer - Design Verification

3 Months ago • 4-6 Years • Software Development & Engineering

Job Summary

Job Description

The Principal Application Engineer will collaborate with the Sales team to identify and evaluate opportunities for Cadence SoC Verification solutions, simulation, Emulation, and Acceleration products. They will manage technical evaluations and benchmarks with customers, provide training and support, and offer technical expertise to address client inquiries. This role requires strong communication skills and collaboration with corporate engineering and sales/marketing teams to align product development with customer requirements. This position requires strong verbal and written communication skills in Japanese and Business-level English proficiency is preferred.
Must have:
  • Design experience in Verilog/VHDL for IP or SoC chip level.
  • Verification knowledge of System Verilog/VHDL and HDL simulators.
  • Experience of using formal verification (JasperGold experience is a plus).
  • Strong verbal and written communication skills in Japanese.
Good to have:
  • Experience with Advanced Verification Methodology like UVM is a plus.

Job Details

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Responsibility:

1. Work closely with the Sales team to identify and scope opportunities for Cadence SoC Verification solution, simulation Emulation and Acceleration products.

2. Plan, execute and manage key technical evaluations and benchmark with existing and potential customers.

3. Train, ramp-up and accompany customer project.

4. Conduct basic and advanced trainings, presentations and demos as necessary.

5. Providing technical expertise to address clients’ queries, which need expert involvement.

6. Aligned closely with corporate engineering and sales/marketing team on customer requirement for product direction/improvement.

Job Requirements:

4-6 or above years’ experience in the following areas:

1. Design experience in Verilog/VHDL for IP or SoC chip level.

2. Verification with knowledge of System Verilog/VHDL and HDL simulators.

3. Experience of using formal verification, JasperGold experience is a plus.

4. Advanced Verification Methodology like UVM is a plus.

5. Strong verbal and written communication skills in Japanese is needed.

6. Business-level English proficiency is preferred.

7. Strong teamwork skills with good human relationship.

We’re doing work that matters. Help us solve what others can’t.

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About The Company

Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

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