Principal Design Engineer

3 Months ago • 5 Years + • Research & Development • Undisclosed

About the job

required for this role

Add these skills to join the top 1% applicants for this job

Job Description

Design state-of-the-art DDR memory controllers for Datacenter, Edge computing, Automotive, and AI. Must have RTL design experience with Verilog, synthesis, lint, and formal verification. Scripting language experience is a plus.

Must have:

RTL design
Verilog, synthesis
Lint, formal
Strong communication

Good to have:

Scripting language
Design Automation
IP development
High speed circuits

Perks:

Leading provider
Impact on technology

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This is an opportunity to join a development team designing state-of-the-art DDR memory controllers to be used in a wide range of applications including Datacenter, Edge computing, Automotive, and AI. Cadence is a leading provider of IP solutions for the biggest names in the technology industry. As a member of our team you will have the following responsibilities:

Architect solutions for the latest DDR controller features and customer requirements
Design RTL in a highly configurable and automated environment
Work in small project teams
Work across disciplines with Design Verification, Support, Delivery, Application Engineers, PHY design team, etc.
Utilize Cadence’s Design Automation flow and IP development tools
Develop high speed circuits and low power features
Improve quality and efficiency and help refine development process for greater productivity of the team through automation and improved methods
Participate in an engineering team to advance our product

Required Experience & Qualifications