Principal Design Engineer

3 Months ago • 7-13 Years
Software Development & Engineering

Job Description

This Principal Design Engineer position at Cadence involves design verification for the IP development team in Bangalore. The role requires developing UVM testbenches for verifying Serial and Interface Design IPs such as PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, and I3C. The responsibilities include creating detailed verification strategies, test plans, and potentially participating in formal verification and emulation qualification. The ideal candidate should possess strong problem-solving, analytical, and debug skills, excellent communication skills, and a passion for delivering high-quality work on time.
Must Have:
  • Verification of Serial and Interface Design IPs (PCIe, CCIX, CXL, etc.).
  • UVM testbench development for design IP verification.
  • Strong problem-solving and analytical skills.
  • Excellent verbal and written communication skills.

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

BE/BTECH/ME/MTECH Or Equivalent Degree

EXP7-13years

Design Verification role for IP development team.

  • Position is based in Bangalore, part of Cadence IP Group.
    Verification role for Serial and Interface Design IPs verification (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C)
  • UVM testbench development to build a robust, scalable and efficient testbench to verify the design IPs.
  • In addition to UVM functional verification, role could involve Formal verification of complex design modules.
  • In addition to UVM functional verification, role could involve participating in Emulation qualification of design IPs.
  • Understand design and produce detailed verification strategy and test plan.
    Self-starter and learner with passion for getting the job done on time with great quality.
  • Strong problem solving, analytical and debug skills
  • Excellent verbal and written communications skills

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