You will manage the design / RTL team to achieve the project goals
You will work with customer, provide technical support and provide collaterals agreed upon.
You will work with team to achieve flow, methodology improvements to achieve high reuse.
You will work with IP vendors to generate / get right configurations of the IP.
You will manage teamwork allocation, schedule, risk mitigation and deliverables from design team.
Interact closely with the architecture team and develop implementation strategies to meet quality, schedule, and power performance area for the SOC.
Interact with the subsystem team and plan SOC milestones, plan quality checks as part of SOC milestones and guide subsystem teams with SOC level requirements (e.g., IPXACT, CSR, Lint, CDC, SDC, UPF, etc.).
Work with the cross-functional team of verification, DFT, Physical Design, emulation, and software teams to make design decisions and represent Design status throughout the development process.
Education: Bachelor's or master's degree in electrical or Electronics and Communication or Computer Science Engineering.
Experience: 15+ years of proven experience in SoC architecture, development, and full-chip design for multi-million gate SoCs.
Expertise:
Strong understanding of the design convergence cycle, including architecture, micro-architecture, verification, synthesis and timing closure.
Expertise in managing IP dependencies, as well as planning and tracking front-end design tasks.
Ability to drive project milestones across design, verification, and physical implementation phases.
Experience in CPU, high-speed serial interfaces, or coherence/noncoherent NOC domains is highly desirable.
Skills:
Excellent communication and interpersonal skills.
Ability to collaborate in a fast-paced, product-oriented, and distributed team environment.
SoC Design Experience: Minimum 15+years of hands-on experience in SoC design.
Architecture Development: Ability to develop architecture and micro-architecture based on specifications.
Bus Protocols & Peripherals: Strong knowledge of bus protocols such as AHB, AXI, and peripherals like PCIe, USB, Ethernet, etc.
Memory Controllers & Microprocessors: Experience with memory controller designs and microprocessors is an advantage.
Chip IO Design: Knowledge of chip IO design and packaging is beneficial.
Test Plans & Verification: Proficient in reviewing high-level test plans and coverage metrics.
Synthesis & Formal Verification: Expertise in Design Compiler Synthesis and formal verification using LEC.
Timing Closure: Comprehensive understanding of timing closure is mandatory.
Post-Silicon Debug: Experience in post-silicon bring-up and debugging.
Decision Making: Ability to make effective decisions under incomplete information.
Communication & Leadership: Strong leadership and communication skills to ensure effective program execution.
As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes:
Great compensation package
Restricted Stock Units (RSUs)
Hybrid Working Model
Provisions to pursue advanced education from Premium Institute, eLearning content providers
Medical Insurance and a cohort of Wellness Benefits
Educational Assistance
Advance Loan Assistance
Office lunch & Snacks Facility
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